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https://github.com/brain-hackers/u-boot-brain
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8627733941
The ti816x/am389x SoC is the first generation in what U-Boot calls the "am33xx" family. In the first generation of this family the DDR initialization sequence is quite different from all of the subsequent generations. Whereas with ti814x (second generation) we can easily work the minor differenced between that and am33xx (third generation), our attempts to do this for ti816x weren't sufficient. Rather than add a large amount of #ifdef logic to make this different sequence work we add a new file, ti816x_emif4.c to handle the various required undocumented register writes and sequence and leverage what we can from arch/arm/mach-omap2/am33xx/ddr.c still. As DDR2 has similar problems today but I am unable to test it, we drop the DDR2 defines from the code rather than imply that it works by leaving it. We also remove a bunch of other untested code about changing the speed the DDR runs at. Signed-off-by: Tom Rini <trini@konsulko.com>
120 lines
3.3 KiB
C
120 lines
3.3 KiB
C
/*
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* ti816x_evm.h
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*
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* Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
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* Antoine Tenart, <atenart@adeneo-embedded.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __CONFIG_TI816X_EVM_H
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#define __CONFIG_TI816X_EVM_H
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#define CONFIG_TI81XX
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#define CONFIG_TI816X
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#define CONFIG_ARCH_CPU_INIT
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#include <asm/arch/omap.h>
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#define CONFIG_ENV_SIZE 0x2000
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (32 * 1024))
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#define CONFIG_SYS_LONGHELP /* undef save memory */
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#define CONFIG_MACH_TYPE MACH_TYPE_TI8168EVM
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#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
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#define CONFIG_SETUP_MEMORY_TAGS
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#define CONFIG_INITRD_TAG /* required for ramdisk support */
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"loadaddr=0x81000000\0" \
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#define CONFIG_BOOTCOMMAND \
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"mmc rescan;" \
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"fatload mmc 0 ${loadaddr} uImage;" \
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"bootm ${loadaddr}" \
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#define CONFIG_BOOTARGS "console=ttyO2,115200n8 noinitrd earlyprintk"
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/* Clock Defines */
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#define V_OSCK 24000000 /* Clock output from T2 */
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#define V_SCLK (V_OSCK >> 1)
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#define CONFIG_SYS_MAXARGS 32
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#define CONFIG_SYS_CBSIZE 512 /* console I/O buffer size */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
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+ sizeof(CONFIG_SYS_PROMPT) + 16) /* print buffer size */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* boot arg buffer size */
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#define CONFIG_SYS_LOAD_ADDR 0x81000000 /* Default load address */
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#define CONFIG_CMD_ASKENV
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#define CONFIG_NR_DRAM_BANKS 2 /* we have 2 banks of DRAM */
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#define PHYS_DRAM_1 0x80000000 /* DRAM Bank #1 */
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#define PHYS_DRAM_1_SIZE 0x40000000 /* 1 GB */
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#define PHYS_DRAM_2 0xC0000000 /* DRAM Bank #2 */
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#define PHYS_DRAM_2_SIZE 0x40000000 /* 1 GB */
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#define CONFIG_MAX_RAM_BANK_SIZE (2048 << 20) /* 2048MB */
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#define CONFIG_SYS_SDRAM_BASE PHYS_DRAM_1
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#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \
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GENERATED_GBL_DATA_SIZE)
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/**
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* Platform/Board specific defs
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*/
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#define CONFIG_SYS_CLK_FREQ 27000000
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#define CONFIG_SYS_TIMERBASE 0x4802E000
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#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
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#undef CONFIG_NAND_OMAP_GPMC
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/*
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* NS16550 Configuration
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*/
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE (-4)
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#define CONFIG_SYS_NS16550_CLK (48000000)
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#define CONFIG_SYS_NS16550_COM1 0x48024000 /* Base EVM has UART2 */
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/* allow overwriting serial config and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_SERIAL1
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#define CONFIG_SERIAL2
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#define CONFIG_SERIAL3
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#define CONFIG_CONS_INDEX 1
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#define CONFIG_ENV_IS_NOWHERE
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/* SPL */
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/* Defines for SPL */
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#define CONFIG_SPL_FRAMEWORK
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#define CONFIG_SPL_TEXT_BASE 0x40400000
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#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
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CONFIG_SPL_TEXT_BASE)
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#define CONFIG_SPL_BSS_START_ADDR 0x80000000
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#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
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#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
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#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
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#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
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#define CONFIG_SYS_SPI_U_BOOT_SIZE 0x40000
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#define CONFIG_SPL_LDSCRIPT "arch/arm/mach-omap2/u-boot-spl.lds"
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#define CONFIG_SYS_TEXT_BASE 0x80800000
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#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
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#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
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/* Since SPL did pll and ddr initialization for us,
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* we don't need to do it twice.
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*/
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#ifndef CONFIG_SPL_BUILD
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#define CONFIG_SKIP_LOWLEVEL_INIT
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#endif
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#endif
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