mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-23 03:19:43 +09:00
8627733941
The ti816x/am389x SoC is the first generation in what U-Boot calls the "am33xx" family. In the first generation of this family the DDR initialization sequence is quite different from all of the subsequent generations. Whereas with ti814x (second generation) we can easily work the minor differenced between that and am33xx (third generation), our attempts to do this for ti816x weren't sufficient. Rather than add a large amount of #ifdef logic to make this different sequence work we add a new file, ti816x_emif4.c to handle the various required undocumented register writes and sequence and leverage what we can from arch/arm/mach-omap2/am33xx/ddr.c still. As DDR2 has similar problems today but I am unable to test it, we drop the DDR2 defines from the code rather than imply that it works by leaving it. We also remove a bunch of other untested code about changing the speed the DDR runs at. Signed-off-by: Tom Rini <trini@konsulko.com>
109 lines
2.8 KiB
C
109 lines
2.8 KiB
C
/*
|
|
* evm.c
|
|
*
|
|
* Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com>
|
|
* Antoine Tenart, <atenart@adeneo-embedded.com>
|
|
*
|
|
* SPDX-License-Identifier: GPL-2.0+
|
|
*/
|
|
|
|
#include <common.h>
|
|
#include <spl.h>
|
|
#include <asm/cache.h>
|
|
#include <asm/io.h>
|
|
#include <asm/arch/clock.h>
|
|
#include <asm/arch/cpu.h>
|
|
#include <asm/arch/ddr_defs.h>
|
|
#include <asm/arch/hardware.h>
|
|
#include <asm/arch/sys_proto.h>
|
|
#include <asm/arch/mmc_host_def.h>
|
|
#include <asm/arch/mem.h>
|
|
#include <asm/arch/mux.h>
|
|
|
|
DECLARE_GLOBAL_DATA_PTR;
|
|
|
|
int board_init(void)
|
|
{
|
|
gd->bd->bi_boot_params = PHYS_DRAM_1 + 0x100;
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_SPL_BUILD
|
|
|
|
static struct module_pin_mux mmc_pin_mux[] = {
|
|
{ OFFSET(pincntl157), PULLDOWN_EN | PULLUDDIS | MODE(0x0) },
|
|
{ OFFSET(pincntl158), PULLDOWN_EN | PULLUDEN | MODE(0x0) },
|
|
{ OFFSET(pincntl159), PULLUP_EN | PULLUDDIS | MODE(0x0) },
|
|
{ OFFSET(pincntl160), PULLUP_EN | PULLUDDIS | MODE(0x0) },
|
|
{ OFFSET(pincntl161), PULLUP_EN | PULLUDDIS | MODE(0x0) },
|
|
{ OFFSET(pincntl162), PULLUP_EN | PULLUDDIS | MODE(0x0) },
|
|
{ OFFSET(pincntl163), PULLUP_EN | PULLUDDIS | MODE(0x0) },
|
|
{ -1 },
|
|
};
|
|
|
|
void set_uart_mux_conf(void) {}
|
|
|
|
void set_mux_conf_regs(void)
|
|
{
|
|
configure_module_pin_mux(mmc_pin_mux);
|
|
}
|
|
|
|
/*
|
|
* EMIF Paramters. Refer the EMIF register documentation and the
|
|
* memory datasheet for details. This is for 796 MHz.
|
|
*/
|
|
#define EMIF_TIM1 0x1779C9FE
|
|
#define EMIF_TIM2 0x50608074
|
|
#define EMIF_TIM3 0x009F857F
|
|
#define EMIF_SDREF 0x10001841
|
|
#define EMIF_SDCFG 0x62A73832
|
|
#define EMIF_PHYCFG 0x00000110
|
|
static const struct emif_regs ddr3_emif_regs = {
|
|
.sdram_config = EMIF_SDCFG,
|
|
.ref_ctrl = EMIF_SDREF,
|
|
.sdram_tim1 = EMIF_TIM1,
|
|
.sdram_tim2 = EMIF_TIM2,
|
|
.sdram_tim3 = EMIF_TIM3,
|
|
.emif_ddr_phy_ctlr_1 = EMIF_PHYCFG,
|
|
};
|
|
|
|
static const struct cmd_control ddr3_ctrl = {
|
|
.cmd0csratio = 0x100,
|
|
.cmd0iclkout = 0x001,
|
|
.cmd1csratio = 0x100,
|
|
.cmd1iclkout = 0x001,
|
|
.cmd2csratio = 0x100,
|
|
.cmd2iclkout = 0x001,
|
|
};
|
|
|
|
/* These values are obtained from the CCS app */
|
|
#define RD_DQS_GATE (0x1B3)
|
|
#define RD_DQS (0x35)
|
|
#define WR_DQS (0x93)
|
|
static struct ddr_data ddr3_data = {
|
|
.datardsratio0 = ((RD_DQS<<10) | (RD_DQS<<0)),
|
|
.datawdsratio0 = ((WR_DQS<<10) | (WR_DQS<<0)),
|
|
.datawiratio0 = ((0x20<<10) | 0x20<<0),
|
|
.datagiratio0 = ((0x20<<10) | 0x20<<0),
|
|
.datafwsratio0 = ((RD_DQS_GATE<<10) | (RD_DQS_GATE<<0)),
|
|
.datawrsratio0 = (((WR_DQS+0x40)<<10) | ((WR_DQS+0x40)<<0)),
|
|
};
|
|
|
|
static const struct dmm_lisa_map_regs evm_lisa_map_regs = {
|
|
.dmm_lisa_map_0 = 0x00000000,
|
|
.dmm_lisa_map_1 = 0x00000000,
|
|
.dmm_lisa_map_2 = 0x80640300,
|
|
.dmm_lisa_map_3 = 0xC0640320,
|
|
};
|
|
|
|
void sdram_init(void)
|
|
{
|
|
/*
|
|
* Pass in our DDR3 config information and that we have 2 EMIFs to
|
|
* configure.
|
|
*/
|
|
config_ddr(&ddr3_data, &ddr3_ctrl, &ddr3_emif_regs,
|
|
&evm_lisa_map_regs, 2);
|
|
}
|
|
#endif /* CONFIG_SPL_BUILD */
|