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https://github.com/brain-hackers/u-boot-brain
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8627733941
The ti816x/am389x SoC is the first generation in what U-Boot calls the "am33xx" family. In the first generation of this family the DDR initialization sequence is quite different from all of the subsequent generations. Whereas with ti814x (second generation) we can easily work the minor differenced between that and am33xx (third generation), our attempts to do this for ti816x weren't sufficient. Rather than add a large amount of #ifdef logic to make this different sequence work we add a new file, ti816x_emif4.c to handle the various required undocumented register writes and sequence and leverage what we can from arch/arm/mach-omap2/am33xx/ddr.c still. As DDR2 has similar problems today but I am unable to test it, we drop the DDR2 defines from the code rather than imply that it works by leaving it. We also remove a bunch of other untested code about changing the speed the DDR runs at. Signed-off-by: Tom Rini <trini@konsulko.com> |
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| .. | ||
| am33xx | ||
| omap3 | ||
| omap4 | ||
| omap5 | ||
| abb.c | ||
| boot-common.c | ||
| clocks-common.c | ||
| config_secure.mk | ||
| config.mk | ||
| emif-common.c | ||
| hwinit-common.c | ||
| Kconfig | ||
| lowlevel_init.S | ||
| Makefile | ||
| mem-common.c | ||
| omap-cache.c | ||
| pipe3-phy.c | ||
| pipe3-phy.h | ||
| reset.c | ||
| sata.c | ||
| sec-common.c | ||
| timer.c | ||
| u-boot-spl.lds | ||
| utils.c | ||
| vc.c | ||