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![Sumit Garg](/assets/img/avatar_default.png)
As part of Chain of Trust for Secure boot, the SPL U-Boot will validate the next level U-boot image. Add a new function spl_validate_uboot to perform the validation. Enable hardware crypto operations in SPL using SEC block. In case of Secure Boot, PAMU is not bypassed. For allowing SEC block access to CPC configured as SRAM, configure PAMU. Reviewed-by: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: York Sun <york.sun@nxp.com>
308 lines
7.5 KiB
C
308 lines
7.5 KiB
C
/*
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* NAND boot for Freescale Integrated Flash Controller, NAND FCM
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*
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* Copyright 2011 Freescale Semiconductor, Inc.
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* Author: Dipen Dudhat <dipen.dudhat@freescale.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <fsl_ifc.h>
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#include <linux/mtd/nand.h>
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#ifdef CONFIG_CHAIN_OF_TRUST
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#include <fsl_validate.h>
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#endif
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static inline int is_blank(uchar *addr, int page_size)
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{
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int i;
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for (i = 0; i < page_size; i++) {
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if (__raw_readb(&addr[i]) != 0xff)
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return 0;
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}
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/*
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* For the SPL, don't worry about uncorrectable errors
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* where the main area is all FFs but shouldn't be.
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*/
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return 1;
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}
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/* returns nonzero if entire page is blank */
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static inline int check_read_ecc(uchar *buf, u32 *eccstat,
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unsigned int bufnum, int page_size)
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{
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u32 reg = eccstat[bufnum / 4];
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int errors = (reg >> ((3 - bufnum % 4) * 8)) & 0xf;
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if (errors == 0xf) { /* uncorrectable */
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/* Blank pages fail hw ECC checks */
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if (is_blank(buf, page_size))
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return 1;
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puts("ecc error\n");
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for (;;)
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;
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}
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return 0;
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}
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static inline struct fsl_ifc_runtime *runtime_regs_address(void)
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{
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struct fsl_ifc regs = {(void *)CONFIG_SYS_IFC_ADDR, NULL};
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int ver = 0;
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ver = ifc_in32(®s.gregs->ifc_rev);
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if (ver >= FSL_IFC_V2_0_0)
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regs.rregs = (void *)CONFIG_SYS_IFC_ADDR + IFC_RREGS_64KOFFSET;
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else
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regs.rregs = (void *)CONFIG_SYS_IFC_ADDR + IFC_RREGS_4KOFFSET;
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return regs.rregs;
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}
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static inline void nand_wait(uchar *buf, int bufnum, int page_size)
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{
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struct fsl_ifc_runtime *ifc = runtime_regs_address();
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u32 status;
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u32 eccstat[8];
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int bufperpage = page_size / 512;
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int bufnum_end, i;
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bufnum *= bufperpage;
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bufnum_end = bufnum + bufperpage - 1;
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do {
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status = ifc_in32(&ifc->ifc_nand.nand_evter_stat);
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} while (!(status & IFC_NAND_EVTER_STAT_OPC));
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if (status & IFC_NAND_EVTER_STAT_FTOER) {
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puts("flash time out error\n");
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for (;;)
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;
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}
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for (i = bufnum / 4; i <= bufnum_end / 4; i++)
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eccstat[i] = ifc_in32(&ifc->ifc_nand.nand_eccstat[i]);
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for (i = bufnum; i <= bufnum_end; i++) {
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if (check_read_ecc(buf, eccstat, i, page_size))
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break;
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}
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ifc_out32(&ifc->ifc_nand.nand_evter_stat, status);
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}
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static inline int bad_block(uchar *marker, int port_size)
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{
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if (port_size == 8)
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return __raw_readb(marker) != 0xff;
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else
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return __raw_readw((u16 *)marker) != 0xffff;
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}
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int nand_spl_load_image(uint32_t offs, unsigned int uboot_size, void *vdst)
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{
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struct fsl_ifc_fcm *gregs = (void *)CONFIG_SYS_IFC_ADDR;
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struct fsl_ifc_runtime *ifc = NULL;
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uchar *buf = (uchar *)CONFIG_SYS_NAND_BASE;
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int page_size;
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int port_size;
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int pages_per_blk;
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int blk_size;
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int bad_marker = 0;
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int bufnum_mask, bufnum, ver = 0;
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int csor, cspr;
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int pos = 0;
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int j = 0;
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int sram_addr;
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int pg_no;
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uchar *dst = vdst;
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ifc = runtime_regs_address();
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/* Get NAND Flash configuration */
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csor = CONFIG_SYS_NAND_CSOR;
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cspr = CONFIG_SYS_NAND_CSPR;
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port_size = (cspr & CSPR_PORT_SIZE_16) ? 16 : 8;
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if ((csor & CSOR_NAND_PGS_MASK) == CSOR_NAND_PGS_8K) {
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page_size = 8192;
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bufnum_mask = 0x0;
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} else if ((csor & CSOR_NAND_PGS_MASK) == CSOR_NAND_PGS_4K) {
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page_size = 4096;
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bufnum_mask = 0x1;
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} else if ((csor & CSOR_NAND_PGS_MASK) == CSOR_NAND_PGS_2K) {
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page_size = 2048;
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bufnum_mask = 0x3;
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} else {
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page_size = 512;
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bufnum_mask = 0xf;
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if (port_size == 8)
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bad_marker = 5;
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}
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ver = ifc_in32(&gregs->ifc_rev);
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if (ver >= FSL_IFC_V2_0_0)
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bufnum_mask = (bufnum_mask * 2) + 1;
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pages_per_blk =
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32 << ((csor & CSOR_NAND_PB_MASK) >> CSOR_NAND_PB_SHIFT);
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blk_size = pages_per_blk * page_size;
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/* Open Full SRAM mapping for spare are access */
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ifc_out32(&ifc->ifc_nand.ncfgr, 0x0);
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/* Clear Boot events */
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ifc_out32(&ifc->ifc_nand.nand_evter_stat, 0xffffffff);
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/* Program FIR/FCR for Large/Small page */
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if (page_size > 512) {
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ifc_out32(&ifc->ifc_nand.nand_fir0,
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(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
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(IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
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(IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
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(IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) |
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(IFC_FIR_OP_BTRD << IFC_NAND_FIR0_OP4_SHIFT));
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ifc_out32(&ifc->ifc_nand.nand_fir1, 0x0);
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ifc_out32(&ifc->ifc_nand.nand_fcr0,
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(NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) |
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(NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT));
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} else {
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ifc_out32(&ifc->ifc_nand.nand_fir0,
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(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
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(IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
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(IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
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(IFC_FIR_OP_BTRD << IFC_NAND_FIR0_OP3_SHIFT));
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ifc_out32(&ifc->ifc_nand.nand_fir1, 0x0);
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ifc_out32(&ifc->ifc_nand.nand_fcr0,
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NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT);
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}
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/* Program FBCR = 0 for full page read */
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ifc_out32(&ifc->ifc_nand.nand_fbcr, 0);
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/* Read and copy u-boot on SDRAM from NAND device, In parallel
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* check for Bad block if found skip it and read continue to
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* next Block
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*/
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while (pos < uboot_size) {
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int i = 0;
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do {
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pg_no = offs / page_size;
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bufnum = pg_no & bufnum_mask;
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sram_addr = bufnum * page_size * 2;
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ifc_out32(&ifc->ifc_nand.row0, pg_no);
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ifc_out32(&ifc->ifc_nand.col0, 0);
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/* start read */
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ifc_out32(&ifc->ifc_nand.nandseq_strt,
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IFC_NAND_SEQ_STRT_FIR_STRT);
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/* wait for read to complete */
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nand_wait(&buf[sram_addr], bufnum, page_size);
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/*
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* If either of the first two pages are marked bad,
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* continue to the next block.
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*/
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if (i++ < 2 &&
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bad_block(&buf[sram_addr + page_size + bad_marker],
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port_size)) {
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puts("skipping\n");
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offs = (offs + blk_size) & ~(blk_size - 1);
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pos &= ~(blk_size - 1);
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break;
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}
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for (j = 0; j < page_size; j++)
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dst[pos + j] = __raw_readb(&buf[sram_addr + j]);
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pos += page_size;
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offs += page_size;
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} while ((offs & (blk_size - 1)) && (pos < uboot_size));
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}
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return 0;
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}
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/*
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* Main entrypoint for NAND Boot. It's necessary that SDRAM is already
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* configured and available since this code loads the main U-Boot image
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* from NAND into SDRAM and starts from there.
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*/
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void nand_boot(void)
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{
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__attribute__((noreturn)) void (*uboot)(void);
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/*
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* Load U-Boot image from NAND into RAM
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*/
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nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS,
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CONFIG_SYS_NAND_U_BOOT_SIZE,
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(uchar *)CONFIG_SYS_NAND_U_BOOT_DST);
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#ifdef CONFIG_NAND_ENV_DST
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nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
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(uchar *)CONFIG_NAND_ENV_DST);
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#ifdef CONFIG_ENV_OFFSET_REDUND
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nand_spl_load_image(CONFIG_ENV_OFFSET_REDUND, CONFIG_ENV_SIZE,
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(uchar *)CONFIG_NAND_ENV_DST + CONFIG_ENV_SIZE);
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#endif
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#endif
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/*
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* Jump to U-Boot image
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*/
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#ifdef CONFIG_SPL_FLUSH_IMAGE
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/*
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* Clean d-cache and invalidate i-cache, to
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* make sure that no stale data is executed.
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*/
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flush_cache(CONFIG_SYS_NAND_U_BOOT_DST, CONFIG_SYS_NAND_U_BOOT_SIZE);
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#endif
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#ifdef CONFIG_CHAIN_OF_TRUST
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/*
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* U-Boot header is appended at end of U-boot image, so
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* calculate U-boot header address using U-boot header size.
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*/
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#define CONFIG_U_BOOT_HDR_ADDR \
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((CONFIG_SYS_NAND_U_BOOT_START + \
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CONFIG_SYS_NAND_U_BOOT_SIZE) - \
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CONFIG_U_BOOT_HDR_SIZE)
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spl_validate_uboot(CONFIG_U_BOOT_HDR_ADDR,
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CONFIG_SYS_NAND_U_BOOT_START);
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/*
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* In case of failure in validation, spl_validate_uboot would
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* not return back in case of Production environment with ITS=1.
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* Thus U-Boot will not start.
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* In Development environment (ITS=0 and SB_EN=1), the function
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* may return back in case of non-fatal failures.
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*/
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#endif
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uboot = (void *)CONFIG_SYS_NAND_U_BOOT_START;
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uboot();
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}
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#ifndef CONFIG_SPL_NAND_INIT
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void nand_init(void)
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{
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}
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void nand_deselect(void)
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{
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}
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#endif
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