mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-02 08:13:44 +09:00
0bd20207ab
The Boot ROM has enabled D-cache and MMU setting DDR memory area as Normal Memory in its page table. Disable D-cache and MMU before jumping to U-Boot proper. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
58 lines
813 B
C
58 lines
813 B
C
/*
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* Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <spl.h>
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#include "../init.h"
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#include "../micro-support-card.h"
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int uniphier_ld20_init(const struct uniphier_board_data *bd)
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{
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uniphier_sbc_init_savepin(bd);
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uniphier_pxs2_sbc_init(bd);
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uniphier_ld20_early_pin_init(bd);
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support_card_reset();
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support_card_init();
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led_puts("L0");
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memconf_init(bd);
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uniphier_pxs2_memconf_init(bd);
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led_puts("L1");
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uniphier_ld20_early_clk_init(bd);
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led_puts("L2");
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led_puts("L3");
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#ifdef CONFIG_SPL_SERIAL_SUPPORT
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preloader_console_init();
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#endif
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led_puts("L4");
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{
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int res;
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res = uniphier_ld20_umc_init(bd);
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if (res < 0) {
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while (1)
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;
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}
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}
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led_puts("L5");
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dcache_disable();
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return 0;
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}
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