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https://github.com/brain-hackers/u-boot-brain
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![Michal Simek](/assets/img/avatar_default.png)
timer support interrupt controller support flash support ethernet support cache support board information support env support booting image support adding support for Xilinx ML401
69 lines
1.8 KiB
ArmAsm
69 lines
1.8 KiB
ArmAsm
/*
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* (C) Copyright 2007 Michal Simek
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*
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* Michal SIMEK <monstr@monstr.eu>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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.text
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.globl dcache_enable
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.ent dcache_enable
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.align 2
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dcache_enable:
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/* Make space on stack for a temporary */
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addi r1, r1, -4
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/* Save register r12 */
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swi r12, r1, 0
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/* Read the MSR register */
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mfs r12, rmsr
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/* Set the instruction enable bit */
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ori r12, r12, 0x80
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/* Save the MSR register */
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mts rmsr, r12
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/* Load register r12 */
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lwi r12, r1, 0
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/* Return */
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rtsd r15, 8
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/* Update stack in the delay slot */
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addi r1, r1, 4
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.end dcache_enable
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.text
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.globl dcache_disable
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.ent dcache_disable
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.align 2
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dcache_disable:
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/* Make space on stack for a temporary */
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addi r1, r1, -4
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/* Save register r12 */
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swi r12, r1, 0
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/* Read the MSR register */
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mfs r12, rmsr
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/* Clear the data cache enable bit */
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andi r12, r12, ~0x80
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/* Save the MSR register */
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mts rmsr, r12
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/* Load register r12 */
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lwi r12, r1, 0
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/* Return */
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rtsd r15, 8
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/* Update stack in the delay slot */
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addi r1, r1, 4
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.end dcache_disable
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