mirror of
https://github.com/brain-hackers/u-boot-brain
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83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
99 lines
3.6 KiB
C
99 lines
3.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* bur_am335x_common.h
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*
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* common parts used by B&R AM335x based boards
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*
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* Copyright (C) 2016 Hannes Schmelzer <oe5hpm@oevsv.at> -
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* Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
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*/
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#ifndef __BUR_AM335X_COMMON_H__
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#define __BUR_AM335X_COMMON_H__
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/* ------------------------------------------------------------------------- */
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#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1GB */
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/* Timer information */
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#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
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#define CONFIG_SYS_TIMERBASE 0x48040000 /* Use Timer2 */
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#define CONFIG_POWER_TPS65217
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#include <asm/arch/omap.h>
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/* NS16550 Configuration */
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE (-4)
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#define CONFIG_SYS_NS16550_CLK 48000000
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#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */
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/* Network defines */
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#define CONFIG_MII /* Required in net/eth.c */
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#define CONFIG_PHY_NATSEMI
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/*
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* SPL related defines. The Public RAM memory map the ROM defines the
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* area between 0x402F0400 and 0x4030B800 as a download area and
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* 0x4030B800 to 0x4030CE00 as a public stack area. The ROM also
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* supports X-MODEM loading via UART, and we leverage this and then use
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* Y-MODEM to load u-boot.img, when booted over UART. We must also include
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* the scratch space that U-Boot uses in SRAM.
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*/
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#define CONFIG_SPL_TEXT_BASE 0x402F0400
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#define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
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CONFIG_SPL_TEXT_BASE)
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/*
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* Since SPL did pll and ddr initialization for us,
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* we don't need to do it twice.
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*/
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#if !defined(CONFIG_SPL_BUILD) && !defined(CONFIG_NOR_BOOT)
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#define CONFIG_SKIP_LOWLEVEL_INIT
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#endif /* !CONFIG_SPL_BUILD, ... */
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/*
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* Our DDR memory always starts at 0x80000000 and U-Boot shall have
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* relocated itself to higher in memory by the time this value is used.
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*/
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#define CONFIG_SYS_LOAD_ADDR 0x80000000
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/*
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* ----------------------------------------------------------------------------
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* DDR information. We say (for simplicity) that we have 1 bank,
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* always, even when we have more. We always start at 0x80000000,
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* and we place the initial stack pointer in our SRAM.
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*/
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#define CONFIG_NR_DRAM_BANKS 1
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#define CONFIG_SYS_SDRAM_BASE 0x80000000
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#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \
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GENERATED_GBL_DATA_SIZE)
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/* I2C */
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#define CONFIG_SYS_I2C
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/*
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* Our platforms make use of SPL to initalize the hardware (primarily
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* memory) enough for full U-Boot to be loaded. We also support Falcon
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* Mode so that the Linux kernel can be booted directly from SPL
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* instead, if desired. We make use of the general SPL framework found
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* under common/spl/. Given our generally common memory map, we set a
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* number of related defaults and sizes here.
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*/
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/*
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* Place the image at the start of the ROM defined image space.
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* We limit our size to the ROM-defined downloaded image area, and use the
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* rest of the space for stack. We load U-Boot itself into memory at
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* 0x80800000 for legacy reasons (to not conflict with older SPLs). We
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* have our BSS be placed 1MiB after this, to allow for the default
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* Linux kernel address of 0x80008000 to work, in the Falcon Mode case.
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* We have the SPL malloc pool at the end of the BSS area.
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*
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* ----------------------------------------------------------------------------
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*/
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#define CONFIG_SPL_BSS_START_ADDR 0x80A00000
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#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
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#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \
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CONFIG_SPL_BSS_MAX_SIZE)
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#define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN
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/* General parts of the framework, required. */
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#endif /* ! __BUR_AM335X_COMMON_H__ */
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