mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
331 lines
7.1 KiB
C
331 lines
7.1 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2015 Beckhoff Automation GmbH & Co. KG
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* Patrick Bruenn <p.bruenn@beckhoff.com>
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*
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* Based on <u-boot>/board/freescale/mx53loco/mx53loco.c
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* Copyright (C) 2011 Freescale Semiconductor, Inc.
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*/
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#include <common.h>
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#include <dm.h>
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#include <asm/io.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/iomux-mx53.h>
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#include <asm/arch/clock.h>
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#include <asm/mach-imx/mx5_video.h>
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#include <ACEX1K.h>
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#include <netdev.h>
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#include <i2c.h>
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#include <mmc.h>
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#include <fsl_esdhc.h>
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#include <asm/gpio.h>
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#include <linux/fb.h>
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#include <ipu_pixfmt.h>
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#include <input.h>
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#include <fs.h>
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#include <dm/platform_data/serial_mxc.h>
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enum LED_GPIOS {
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GPIO_SD1_CD = IMX_GPIO_NR(1, 1),
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GPIO_SD2_CD = IMX_GPIO_NR(1, 4),
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GPIO_LED_SD2_R = IMX_GPIO_NR(3, 16),
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GPIO_LED_SD2_B = IMX_GPIO_NR(3, 17),
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GPIO_LED_SD2_G = IMX_GPIO_NR(3, 18),
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GPIO_LED_SD1_R = IMX_GPIO_NR(3, 19),
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GPIO_LED_SD1_B = IMX_GPIO_NR(3, 20),
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GPIO_LED_SD1_G = IMX_GPIO_NR(3, 21),
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GPIO_LED_PWR_R = IMX_GPIO_NR(3, 22),
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GPIO_LED_PWR_B = IMX_GPIO_NR(3, 23),
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GPIO_LED_PWR_G = IMX_GPIO_NR(3, 24),
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GPIO_SUPS_INT = IMX_GPIO_NR(3, 31),
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GPIO_C3_CONFIG = IMX_GPIO_NR(6, 8),
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GPIO_C3_STATUS = IMX_GPIO_NR(6, 7),
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GPIO_C3_DONE = IMX_GPIO_NR(6, 9),
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};
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#define CCAT_BASE_ADDR ((void *)0xf0000000)
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#define CCAT_END_ADDR (CCAT_BASE_ADDR + (1024 * 1024 * 32))
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#define CCAT_SIZE 1191788
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#define CCAT_SIGN_ADDR (CCAT_BASE_ADDR + 12)
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static const char CCAT_SIGNATURE[] = "CCAT";
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static const u32 CCAT_MODE_CONFIG = 0x0024DC81;
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static const u32 CCAT_MODE_RUN = 0x0033DC8F;
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DECLARE_GLOBAL_DATA_PTR;
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u32 get_board_rev(void)
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{
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struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
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struct fuse_bank *bank = &iim->bank[0];
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struct fuse_bank0_regs *fuse =
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(struct fuse_bank0_regs *)bank->fuse_regs;
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int rev = readl(&fuse->gp[6]);
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return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8;
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}
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/*
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* Set CCAT mode
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* @mode: use CCAT_MODE_CONFIG or CCAT_MODE_RUN
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*/
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void weim_cs0_settings(u32 mode)
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{
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struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR;
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writel(0x0, &weim_regs->cs0gcr1);
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writel(mode, &weim_regs->cs0gcr1);
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writel(0x00001002, &weim_regs->cs0gcr2);
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writel(0x04000000, &weim_regs->cs0rcr1);
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writel(0x00000000, &weim_regs->cs0rcr2);
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writel(0x04000000, &weim_regs->cs0wcr1);
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writel(0x00000000, &weim_regs->cs0wcr2);
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}
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static void setup_gpio_eim(void)
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{
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gpio_direction_input(GPIO_C3_STATUS);
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gpio_direction_input(GPIO_C3_DONE);
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gpio_direction_output(GPIO_C3_CONFIG, 1);
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weim_cs0_settings(CCAT_MODE_RUN);
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}
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static void setup_gpio_sups(void)
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{
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gpio_direction_input(GPIO_SUPS_INT);
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static const int BLINK_INTERVALL = 50000;
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int status = 1;
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while (gpio_get_value(GPIO_SUPS_INT)) {
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/* signal "CX SUPS power fail" */
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gpio_set_value(GPIO_LED_PWR_R,
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(++status / BLINK_INTERVALL) % 2);
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}
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/* signal "CX power up" */
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gpio_set_value(GPIO_LED_PWR_R, 1);
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}
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static void setup_gpio_leds(void)
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{
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gpio_direction_output(GPIO_LED_SD2_R, 0);
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gpio_direction_output(GPIO_LED_SD2_B, 0);
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gpio_direction_output(GPIO_LED_SD2_G, 0);
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gpio_direction_output(GPIO_LED_SD1_R, 0);
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gpio_direction_output(GPIO_LED_SD1_B, 0);
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gpio_direction_output(GPIO_LED_SD1_G, 0);
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gpio_direction_output(GPIO_LED_PWR_R, 0);
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gpio_direction_output(GPIO_LED_PWR_B, 0);
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gpio_direction_output(GPIO_LED_PWR_G, 0);
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}
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#ifdef CONFIG_USB_EHCI_MX5
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int board_ehci_hcd_init(int port)
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{
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/* request VBUS power enable pin, GPIO7_8 */
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gpio_direction_output(IMX_GPIO_NR(7, 8), 1);
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return 0;
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}
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#endif
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#ifdef CONFIG_FSL_ESDHC
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struct fsl_esdhc_cfg esdhc_cfg[2] = {
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{MMC_SDHC1_BASE_ADDR},
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{MMC_SDHC2_BASE_ADDR},
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};
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int board_mmc_getcd(struct mmc *mmc)
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{
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struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
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int ret;
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gpio_direction_input(GPIO_SD1_CD);
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gpio_direction_input(GPIO_SD2_CD);
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if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
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ret = !gpio_get_value(GPIO_SD1_CD);
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else
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ret = !gpio_get_value(GPIO_SD2_CD);
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return ret;
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}
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int board_mmc_init(bd_t *bis)
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{
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u32 index;
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int ret;
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esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
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esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
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for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
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switch (index) {
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case 0:
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break;
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case 1:
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break;
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default:
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printf("Warning: you configured more ESDHC controller(%d) as supported by the board(2)\n",
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CONFIG_SYS_FSL_ESDHC_NUM);
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return -EINVAL;
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}
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ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
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if (ret)
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return ret;
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}
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return 0;
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}
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#endif
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static int power_init(void)
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{
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/* nothing to do on CX9020 */
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return 0;
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}
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static void clock_1GHz(void)
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{
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int ret;
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u32 ref_clk = MXC_HCLK;
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/*
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* After increasing voltage to 1.25V, we can switch
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* CPU clock to 1GHz and DDR to 400MHz safely
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*/
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ret = mxc_set_clock(ref_clk, 1000, MXC_ARM_CLK);
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if (ret)
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printf("CPU: Switch CPU clock to 1GHZ failed\n");
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ret = mxc_set_clock(ref_clk, 400, MXC_PERIPH_CLK);
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ret |= mxc_set_clock(ref_clk, 400, MXC_DDR_CLK);
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if (ret)
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printf("CPU: Switch DDR clock to 400MHz failed\n");
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}
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int board_early_init_f(void)
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{
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setup_gpio_leds();
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setup_gpio_sups();
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setup_gpio_eim();
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setup_iomux_lcd();
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return 0;
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}
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/*
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* Do not overwrite the console
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* Use always serial for U-Boot console
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*/
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int overwrite_console(void)
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{
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return 1;
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}
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int board_init(void)
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{
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gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
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mxc_set_sata_internal_clock();
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return 0;
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}
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int checkboard(void)
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{
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puts("Board: Beckhoff CX9020\n");
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return 0;
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}
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static int ccat_config_fn(int assert_config, int flush, int cookie)
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{
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/* prepare FPGA for programming */
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weim_cs0_settings(CCAT_MODE_CONFIG);
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gpio_set_value(GPIO_C3_CONFIG, 0);
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udelay(1);
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gpio_set_value(GPIO_C3_CONFIG, 1);
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udelay(230);
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return FPGA_SUCCESS;
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}
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static int ccat_status_fn(int cookie)
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{
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return FPGA_FAIL;
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}
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static int ccat_write_fn(const void *buf, size_t buf_len, int flush, int cookie)
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{
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const uint8_t *const buffer = buf;
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/* program CCAT */
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int i;
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for (i = 0; i < buf_len; ++i)
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writeb(buffer[i], CCAT_BASE_ADDR);
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writeb(0xff, CCAT_BASE_ADDR);
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writeb(0xff, CCAT_BASE_ADDR);
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return FPGA_SUCCESS;
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}
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static int ccat_done_fn(int cookie)
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{
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/* programming complete? */
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return gpio_get_value(GPIO_C3_DONE);
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}
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static int ccat_post_fn(int cookie)
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{
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/* switch to FPGA run mode */
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weim_cs0_settings(CCAT_MODE_RUN);
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invalidate_dcache_range((ulong) CCAT_BASE_ADDR, (ulong) CCAT_END_ADDR);
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if (memcmp(CCAT_SIGN_ADDR, CCAT_SIGNATURE, sizeof(CCAT_SIGNATURE))) {
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printf("Verifing CCAT firmware failed, signature not found\n");
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return FPGA_FAIL;
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}
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/* signal "CX booting OS" */
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gpio_set_value(GPIO_LED_PWR_R, 1);
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gpio_set_value(GPIO_LED_PWR_G, 1);
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gpio_set_value(GPIO_LED_PWR_B, 0);
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return FPGA_SUCCESS;
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}
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static Altera_CYC2_Passive_Serial_fns ccat_fns = {
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.config = ccat_config_fn,
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.status = ccat_status_fn,
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.done = ccat_done_fn,
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.write = ccat_write_fn,
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.abort = ccat_post_fn,
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.post = ccat_post_fn,
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};
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static Altera_desc ccat_fpga = {
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.family = Altera_CYC2,
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.iface = passive_serial,
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.size = CCAT_SIZE,
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.iface_fns = &ccat_fns,
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.base = CCAT_BASE_ADDR,
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};
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int board_late_init(void)
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{
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if (!power_init())
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clock_1GHz();
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fpga_init();
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fpga_add(fpga_altera, &ccat_fpga);
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return 0;
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}
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