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https://github.com/brain-hackers/u-boot-brain
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3fda0262c3
This patch adds SiFive FU540 board support. For now, only SiFive serial, SiFive PRCI, and Cadance MACB drivers are only enabled. The SiFive FU540 defconfig by default builds U-Boot for S-Mode because U-Boot on SiFive FU540 will run in S-Mode as payload of BBL or OpenSBI. Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Alexander Graf <agraf@suse.de> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
124 lines
2.4 KiB
Plaintext
124 lines
2.4 KiB
Plaintext
menu "RISC-V architecture"
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depends on RISCV
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config SYS_ARCH
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default "riscv"
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choice
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prompt "Target select"
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optional
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config TARGET_AX25_AE350
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bool "Support ax25-ae350"
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config TARGET_QEMU_VIRT
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bool "Support QEMU Virt Board"
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config TARGET_SIFIVE_FU540
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bool "Support SiFive FU540 Board"
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endchoice
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# board-specific options below
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source "board/AndesTech/ax25-ae350/Kconfig"
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source "board/emulation/qemu-riscv/Kconfig"
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source "board/sifive/fu540/Kconfig"
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# platform-specific options below
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source "arch/riscv/cpu/ax25/Kconfig"
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source "arch/riscv/cpu/generic/Kconfig"
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# architecture-specific options below
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choice
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prompt "Base ISA"
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default ARCH_RV32I
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config ARCH_RV32I
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bool "RV32I"
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select 32BIT
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help
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Choose this option to target the RV32I base integer instruction set.
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config ARCH_RV64I
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bool "RV64I"
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select 64BIT
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select PHYS_64BIT
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help
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Choose this option to target the RV64I base integer instruction set.
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endchoice
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choice
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prompt "Code Model"
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default CMODEL_MEDLOW
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config CMODEL_MEDLOW
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bool "medium low code model"
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help
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U-Boot and its statically defined symbols must lie within a single 2 GiB
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address range and must lie between absolute addresses -2 GiB and +2 GiB.
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config CMODEL_MEDANY
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bool "medium any code model"
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help
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U-Boot and its statically defined symbols must be within any single 2 GiB
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address range.
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endchoice
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choice
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prompt "Run Mode"
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default RISCV_MMODE
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config RISCV_MMODE
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bool "Machine"
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help
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Choose this option to build U-Boot for RISC-V M-Mode.
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config RISCV_SMODE
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bool "Supervisor"
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help
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Choose this option to build U-Boot for RISC-V S-Mode.
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endchoice
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config RISCV_ISA_C
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bool "Emit compressed instructions"
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default y
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help
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Adds "C" to the ISA subsets that the toolchain is allowed to emit
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when building U-Boot, which results in compressed instructions in the
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U-Boot binary.
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config RISCV_ISA_A
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def_bool y
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config 32BIT
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bool
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config 64BIT
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bool
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config SIFIVE_CLINT
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bool
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depends on RISCV_MMODE
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select REGMAP
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select SYSCON
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help
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The SiFive CLINT block holds memory-mapped control and status registers
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associated with software and timer interrupts.
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config RISCV_RDTIME
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bool
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default y if RISCV_SMODE
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help
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The provides the riscv_get_time() API that is implemented using the
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standard rdtime instruction. This is the case for S-mode U-Boot, and
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is useful for processors that support rdtime in M-mode too.
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config SYS_MALLOC_F_LEN
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default 0x1000
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endmenu
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