mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-11 13:46:17 +09:00
b41411954d
U-Boot has never cared about the type when we get max/min of two values, but Linux Kernel does. This commit gets min, max, min3, max3 macros synced with the kernel introducing type checks. Many of references of those macros must be fixed to suppress warnings. We have two options: - Use min, max, min3, max3 only when the arguments have the same type (or add casts to the arguments) - Use min_t/max_t instead with the appropriate type for the first argument Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Pavel Machek <pavel@denx.de> Acked-by: Lukasz Majewski <l.majewski@samsung.com> Tested-by: Lukasz Majewski <l.majewski@samsung.com> [trini: Fixup arch/blackfin/lib/string.c] Signed-off-by: Tom Rini <trini@ti.com>
347 lines
7.0 KiB
C
347 lines
7.0 KiB
C
/*
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* Copyright 2008-2011 Freescale Semiconductor, Inc.
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*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/processor.h>
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#include <asm/mmu.h>
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#ifdef CONFIG_ADDR_MAP
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#include <addr_map.h>
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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void invalidate_tlb(u8 tlb)
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{
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if (tlb == 0)
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mtspr(MMUCSR0, 0x4);
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if (tlb == 1)
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mtspr(MMUCSR0, 0x2);
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}
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__weak void init_tlbs(void)
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{
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int i;
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for (i = 0; i < num_tlb_entries; i++) {
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write_tlb(tlb_table[i].mas0,
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tlb_table[i].mas1,
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tlb_table[i].mas2,
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tlb_table[i].mas3,
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tlb_table[i].mas7);
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}
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return ;
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}
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#if !defined(CONFIG_NAND_SPL) && \
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(!defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL_INIT_MINIMAL))
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void read_tlbcam_entry(int idx, u32 *valid, u32 *tsize, unsigned long *epn,
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phys_addr_t *rpn)
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{
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u32 _mas1;
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mtspr(MAS0, FSL_BOOKE_MAS0(1, idx, 0));
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asm volatile("tlbre;isync");
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_mas1 = mfspr(MAS1);
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*valid = (_mas1 & MAS1_VALID);
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*tsize = (_mas1 >> 7) & 0x1f;
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*epn = mfspr(MAS2) & MAS2_EPN;
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*rpn = mfspr(MAS3) & MAS3_RPN;
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#ifdef CONFIG_ENABLE_36BIT_PHYS
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*rpn |= ((u64)mfspr(MAS7)) << 32;
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#endif
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}
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void print_tlbcam(void)
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{
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int i;
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unsigned int num_cam = mfspr(SPRN_TLB1CFG) & 0xfff;
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/* walk all the entries */
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printf("TLBCAM entries\n");
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for (i = 0; i < num_cam; i++) {
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unsigned long epn;
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u32 tsize, valid;
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phys_addr_t rpn;
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read_tlbcam_entry(i, &valid, &tsize, &epn, &rpn);
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printf("entry %02d: V: %d EPN 0x%08x RPN 0x%08llx size:",
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i, (valid == 0) ? 0 : 1, (unsigned int)epn,
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(unsigned long long)rpn);
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print_size(TSIZE_TO_BYTES(tsize), "\n");
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}
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}
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static inline void use_tlb_cam(u8 idx)
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{
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int i = idx / 32;
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int bit = idx % 32;
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gd->arch.used_tlb_cams[i] |= (1 << bit);
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}
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static inline void free_tlb_cam(u8 idx)
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{
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int i = idx / 32;
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int bit = idx % 32;
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gd->arch.used_tlb_cams[i] &= ~(1 << bit);
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}
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void init_used_tlb_cams(void)
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{
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int i;
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unsigned int num_cam = mfspr(SPRN_TLB1CFG) & 0xfff;
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for (i = 0; i < ((CONFIG_SYS_NUM_TLBCAMS+31)/32); i++)
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gd->arch.used_tlb_cams[i] = 0;
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/* walk all the entries */
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for (i = 0; i < num_cam; i++) {
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mtspr(MAS0, FSL_BOOKE_MAS0(1, i, 0));
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asm volatile("tlbre;isync");
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if (mfspr(MAS1) & MAS1_VALID)
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use_tlb_cam(i);
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}
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}
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int find_free_tlbcam(void)
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{
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int i;
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u32 idx;
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for (i = 0; i < ((CONFIG_SYS_NUM_TLBCAMS+31)/32); i++) {
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idx = ffz(gd->arch.used_tlb_cams[i]);
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if (idx != 32)
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break;
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}
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idx += i * 32;
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if (idx >= CONFIG_SYS_NUM_TLBCAMS)
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return -1;
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return idx;
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}
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void set_tlb(u8 tlb, u32 epn, u64 rpn,
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u8 perms, u8 wimge,
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u8 ts, u8 esel, u8 tsize, u8 iprot)
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{
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u32 _mas0, _mas1, _mas2, _mas3, _mas7;
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if (tlb == 1)
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use_tlb_cam(esel);
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if ((mfspr(SPRN_MMUCFG) & MMUCFG_MAVN) == MMUCFG_MAVN_V1 &&
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tsize & 1) {
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printf("%s: bad tsize %d on entry %d at 0x%08x\n",
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__func__, tsize, tlb, epn);
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return;
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}
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_mas0 = FSL_BOOKE_MAS0(tlb, esel, 0);
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_mas1 = FSL_BOOKE_MAS1(1, iprot, 0, ts, tsize);
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_mas2 = FSL_BOOKE_MAS2(epn, wimge);
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_mas3 = FSL_BOOKE_MAS3(rpn, 0, perms);
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_mas7 = FSL_BOOKE_MAS7(rpn);
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write_tlb(_mas0, _mas1, _mas2, _mas3, _mas7);
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#ifdef CONFIG_ADDR_MAP
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if ((tlb == 1) && (gd->flags & GD_FLG_RELOC))
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addrmap_set_entry(epn, rpn, TSIZE_TO_BYTES(tsize), esel);
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#endif
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}
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void disable_tlb(u8 esel)
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{
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u32 _mas0, _mas1, _mas2, _mas3;
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free_tlb_cam(esel);
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_mas0 = FSL_BOOKE_MAS0(1, esel, 0);
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_mas1 = 0;
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_mas2 = 0;
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_mas3 = 0;
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mtspr(MAS0, _mas0);
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mtspr(MAS1, _mas1);
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mtspr(MAS2, _mas2);
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mtspr(MAS3, _mas3);
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#ifdef CONFIG_ENABLE_36BIT_PHYS
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mtspr(MAS7, 0);
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#endif
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asm volatile("isync;msync;tlbwe;isync");
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#ifdef CONFIG_ADDR_MAP
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if (gd->flags & GD_FLG_RELOC)
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addrmap_set_entry(0, 0, 0, esel);
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#endif
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}
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static void tlbsx (const volatile unsigned *addr)
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{
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__asm__ __volatile__ ("tlbsx 0,%0" : : "r" (addr), "m" (*addr));
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}
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/* return -1 if we didn't find anything */
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int find_tlb_idx(void *addr, u8 tlbsel)
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{
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u32 _mas0, _mas1;
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/* zero out Search PID, AS */
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mtspr(MAS6, 0);
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tlbsx(addr);
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_mas0 = mfspr(MAS0);
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_mas1 = mfspr(MAS1);
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/* we found something, and its in the TLB we expect */
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if ((MAS1_VALID & _mas1) &&
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(MAS0_TLBSEL(tlbsel) == (_mas0 & MAS0_TLBSEL_MSK))) {
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return ((_mas0 & MAS0_ESEL_MSK) >> 16);
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}
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return -1;
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}
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#ifdef CONFIG_ADDR_MAP
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void init_addr_map(void)
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{
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int i;
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unsigned int num_cam = mfspr(SPRN_TLB1CFG) & 0xfff;
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/* walk all the entries */
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for (i = 0; i < num_cam; i++) {
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unsigned long epn;
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u32 tsize, valid;
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phys_addr_t rpn;
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read_tlbcam_entry(i, &valid, &tsize, &epn, &rpn);
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if (valid & MAS1_VALID)
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addrmap_set_entry(epn, rpn, TSIZE_TO_BYTES(tsize), i);
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}
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return ;
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}
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#endif
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uint64_t tlb_map_range(ulong v_addr, phys_addr_t p_addr, uint64_t size,
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enum tlb_map_type map_type)
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{
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int i;
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unsigned int tlb_size;
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unsigned int wimge;
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unsigned int perm;
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unsigned int max_cam, tsize_mask;
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if (map_type == TLB_MAP_RAM) {
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perm = MAS3_SX|MAS3_SW|MAS3_SR;
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wimge = MAS2_M;
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#ifdef CONFIG_SYS_PPC_DDR_WIMGE
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wimge = CONFIG_SYS_PPC_DDR_WIMGE;
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#endif
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} else {
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perm = MAS3_SW|MAS3_SR;
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wimge = MAS2_I|MAS2_G;
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}
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if ((mfspr(SPRN_MMUCFG) & MMUCFG_MAVN) == MMUCFG_MAVN_V1) {
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/* Convert (4^max) kB to (2^max) bytes */
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max_cam = ((mfspr(SPRN_TLB1CFG) >> 16) & 0xf) * 2 + 10;
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tsize_mask = ~1U;
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} else {
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/* Convert (2^max) kB to (2^max) bytes */
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max_cam = __ilog2(mfspr(SPRN_TLB1PS)) + 10;
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tsize_mask = ~0U;
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}
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for (i = 0; size && i < 8; i++) {
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int tlb_index = find_free_tlbcam();
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u32 camsize = __ilog2_u64(size) & tsize_mask;
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u32 align = __ilog2(v_addr) & tsize_mask;
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if (tlb_index == -1)
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break;
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if (align == -2) align = max_cam;
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if (camsize > align)
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camsize = align;
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if (camsize > max_cam)
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camsize = max_cam;
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tlb_size = camsize - 10;
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set_tlb(1, v_addr, p_addr, perm, wimge,
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0, tlb_index, tlb_size, 1);
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size -= 1ULL << camsize;
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v_addr += 1UL << camsize;
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p_addr += 1UL << camsize;
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}
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return size;
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}
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unsigned int setup_ddr_tlbs_phys(phys_addr_t p_addr,
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unsigned int memsize_in_meg)
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{
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unsigned int ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE;
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u64 memsize = (u64)memsize_in_meg << 20;
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memsize = min(memsize, (u64)CONFIG_MAX_MEM_MAPPED);
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memsize = tlb_map_range(ram_tlb_address, p_addr, memsize, TLB_MAP_RAM);
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if (memsize)
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print_size(memsize, " left unmapped\n");
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return memsize_in_meg;
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}
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unsigned int setup_ddr_tlbs(unsigned int memsize_in_meg)
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{
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return
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setup_ddr_tlbs_phys(CONFIG_SYS_DDR_SDRAM_BASE, memsize_in_meg);
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}
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/* Invalidate the DDR TLBs for the requested size */
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void clear_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg)
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{
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u32 vstart = CONFIG_SYS_DDR_SDRAM_BASE;
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unsigned long epn;
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u32 tsize, valid, ptr;
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phys_addr_t rpn = 0;
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int ddr_esel;
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u64 memsize = (u64)memsize_in_meg << 20;
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ptr = vstart;
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while (ptr < (vstart + memsize)) {
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ddr_esel = find_tlb_idx((void *)ptr, 1);
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if (ddr_esel != -1) {
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read_tlbcam_entry(ddr_esel, &valid, &tsize, &epn, &rpn);
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disable_tlb(ddr_esel);
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}
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ptr += TSIZE_TO_BYTES(tsize);
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}
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}
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void clear_ddr_tlbs(unsigned int memsize_in_meg)
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{
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clear_ddr_tlbs_phys(CONFIG_SYS_DDR_SDRAM_BASE, memsize_in_meg);
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}
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#endif /* not SPL */
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