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![Haavard Skinnemoen](/assets/img/avatar_default.png)
This patch gets rid of the spi_chipsel table and adds a handful of new functions that makes the SPI layer cleaner and more flexible. Instead of the spi_chipsel table, each board that wants to use SPI gets to implement three hooks: * spi_cs_activate(): Activates the chipselect for a given slave * spi_cs_deactivate(): Deactivates the chipselect for a given slave * spi_cs_is_valid(): Determines if the given bus/chipselect combination can be activated. Not all drivers may need those extra functions however. If that's the case, the board code may just leave them out (assuming they know what the driver needs) or rely on the linker to strip them out (assuming --gc-sections is being used.) To set up communication parameters for a given slave, the driver needs to call spi_setup_slave(). This returns a pointer to an opaque spi_slave struct which must be passed as a parameter to subsequent SPI calls. This struct can be freed by calling spi_free_slave(), but most driver probably don't want to do this. Before starting one or more SPI transfers, the driver must call spi_claim_bus() to gain exclusive access to the SPI bus and initialize the hardware. When all transfers are done, the driver must call spi_release_bus() to make the bus available to others, and possibly shut down the SPI controller hardware. spi_xfer() behaves mostly the same as before, but it now takes a spi_slave parameter instead of a spi_chipsel function pointer. It also got a new parameter, flags, which is used to specify chip select behaviour. This may be extended with other flags in the future. This patch has been build-tested on all powerpc and arm boards involved. I have not tested NIOS since I don't have a toolchain for it installed, so I expect some breakage there even though I've tried fixing up everything I could find by visual inspection. I have run-time tested this on AVR32 ATNGW100 using the atmel_spi and DataFlash drivers posted as a follow-up. I'd like some help testing other boards that use the existing SPI API. But most of all, I'd like some comments on the new API. Is this stuff usable for everyone? If not, why? Changed in v4: - Build fixes for various boards, drivers and commands - Provide common struct spi_slave definition that can be extended by drivers - Pass a struct spi_slave * to spi_cs_activate and spi_cs_deactivate - Make default bus and mode build-time configurable - Override default SPI bus ID and mode on mx32ads and imx31_litekit. Changed in v3: - Add opaque struct spi_slave for controller-specific data associated with a slave. - Add spi_claim_bus() and spi_release_bus() - Add spi_free_slave() - spi_setup() is now called spi_setup_slave() and returns a struct spi_slave - soft_spi now supports four SPI modes (CPOL|CPHA) - Add bus parameter to spi_setup_slave() - Convert the new i.MX32 SPI driver - Convert the new MC13783 RTC driver Changed in v2: - Convert the mpc8xxx_spi driver and the mpc8349emds board to the new API. Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com> Tested-by: Guennadi Liakhovetski <lg@denx.de>
289 lines
6.6 KiB
C
289 lines
6.6 KiB
C
/*
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* (C) Copyright 2006
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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#include <common.h>
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#include <ioports.h>
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#include <mpc83xx.h>
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#include <asm/mpc8349_pci.h>
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#include <i2c.h>
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#include <spi.h>
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#include <miiphy.h>
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#include <spd_sdram.h>
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#if defined(CONFIG_OF_LIBFDT)
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#include <libfdt.h>
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#endif
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int fixed_sdram(void);
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void sdram_init(void);
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#if defined(CONFIG_DDR_ECC) && defined(CONFIG_MPC83XX)
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void ddr_enable_ecc(unsigned int dram_size);
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#endif
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int board_early_init_f (void)
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{
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volatile u8* bcsr = (volatile u8*)CFG_BCSR;
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/* Enable flash write */
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bcsr[1] &= ~0x01;
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#ifdef CFG_USE_MPC834XSYS_USB_PHY
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/* Use USB PHY on SYS board */
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bcsr[5] |= 0x02;
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#endif
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return 0;
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}
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#define ns2clk(ns) (ns / (1000000000 / CONFIG_8349_CLKIN) + 1)
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long int initdram (int board_type)
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{
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volatile immap_t *im = (immap_t *)CFG_IMMR;
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u32 msize = 0;
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if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
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return -1;
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/* DDR SDRAM - Main SODIMM */
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im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR;
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#if defined(CONFIG_SPD_EEPROM)
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msize = spd_sdram();
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#else
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msize = fixed_sdram();
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#endif
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/*
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* Initialize SDRAM if it is on local bus.
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*/
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sdram_init();
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#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
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/*
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* Initialize and enable DDR ECC.
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*/
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ddr_enable_ecc(msize * 1024 * 1024);
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#endif
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/* return total bus SDRAM size(bytes) -- DDR */
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return (msize * 1024 * 1024);
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}
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#if !defined(CONFIG_SPD_EEPROM)
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/*************************************************************************
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* fixed sdram init -- doesn't use serial presence detect.
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************************************************************************/
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int fixed_sdram(void)
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{
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volatile immap_t *im = (immap_t *)CFG_IMMR;
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u32 msize = 0;
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u32 ddr_size;
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u32 ddr_size_log2;
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msize = CFG_DDR_SIZE;
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for (ddr_size = msize << 20, ddr_size_log2 = 0;
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(ddr_size > 1);
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ddr_size = ddr_size>>1, ddr_size_log2++) {
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if (ddr_size & 1) {
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return -1;
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}
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}
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im->sysconf.ddrlaw[0].bar = ((CFG_DDR_SDRAM_BASE>>12) & 0xfffff);
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im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
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#if (CFG_DDR_SIZE != 256)
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#warning Currenly any ddr size other than 256 is not supported
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#endif
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#ifdef CONFIG_DDR_II
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im->ddr.csbnds[2].csbnds = CFG_DDR_CS2_BNDS;
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im->ddr.cs_config[2] = CFG_DDR_CS2_CONFIG;
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im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0;
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im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
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im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
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im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3;
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im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG;
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im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2;
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im->ddr.sdram_mode = CFG_DDR_MODE;
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im->ddr.sdram_mode2 = CFG_DDR_MODE2;
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im->ddr.sdram_interval = CFG_DDR_INTERVAL;
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im->ddr.sdram_clk_cntl = CFG_DDR_CLK_CNTL;
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#else
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im->ddr.csbnds[2].csbnds = 0x0000000f;
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im->ddr.cs_config[2] = CFG_DDR_CONFIG;
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/* currently we use only one CS, so disable the other banks */
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im->ddr.cs_config[0] = 0;
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im->ddr.cs_config[1] = 0;
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im->ddr.cs_config[3] = 0;
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im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
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im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
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im->ddr.sdram_cfg =
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SDRAM_CFG_SREN
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#if defined(CONFIG_DDR_2T_TIMING)
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| SDRAM_CFG_2T_EN
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#endif
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| 2 << SDRAM_CFG_SDRAM_TYPE_SHIFT;
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#if defined (CONFIG_DDR_32BIT)
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/* for 32-bit mode burst length is 8 */
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im->ddr.sdram_cfg |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE);
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#endif
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im->ddr.sdram_mode = CFG_DDR_MODE;
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im->ddr.sdram_interval = CFG_DDR_INTERVAL;
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#endif
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udelay(200);
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/* enable DDR controller */
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im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
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return msize;
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}
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#endif/*!CFG_SPD_EEPROM*/
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int checkboard (void)
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{
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puts("Board: Freescale MPC8349EMDS\n");
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return 0;
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}
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/*
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* if MPC8349EMDS is soldered with SDRAM
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*/
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#if defined(CFG_BR2_PRELIM) \
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&& defined(CFG_OR2_PRELIM) \
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&& defined(CFG_LBLAWBAR2_PRELIM) \
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&& defined(CFG_LBLAWAR2_PRELIM)
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/*
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* Initialize SDRAM memory on the Local Bus.
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*/
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void sdram_init(void)
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{
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volatile immap_t *immap = (immap_t *)CFG_IMMR;
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volatile lbus83xx_t *lbc= &immap->lbus;
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uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
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/*
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* Setup SDRAM Base and Option Registers, already done in cpu_init.c
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*/
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/* setup mtrpt, lsrt and lbcr for LB bus */
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lbc->lbcr = CFG_LBC_LBCR;
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lbc->mrtpr = CFG_LBC_MRTPR;
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lbc->lsrt = CFG_LBC_LSRT;
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asm("sync");
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/*
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* Configure the SDRAM controller Machine Mode Register.
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*/
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lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation */
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lbc->lsdmr = CFG_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */
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asm("sync");
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*sdram_addr = 0xff;
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udelay(100);
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lbc->lsdmr = CFG_LBC_LSDMR_2; /* 0x48636733; auto refresh */
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asm("sync");
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/*1 times*/
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*sdram_addr = 0xff;
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udelay(100);
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/*2 times*/
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*sdram_addr = 0xff;
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udelay(100);
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/*3 times*/
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*sdram_addr = 0xff;
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udelay(100);
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/*4 times*/
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*sdram_addr = 0xff;
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udelay(100);
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/*5 times*/
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*sdram_addr = 0xff;
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udelay(100);
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/*6 times*/
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*sdram_addr = 0xff;
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udelay(100);
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/*7 times*/
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*sdram_addr = 0xff;
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udelay(100);
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/*8 times*/
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*sdram_addr = 0xff;
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udelay(100);
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/* 0x58636733; mode register write operation */
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lbc->lsdmr = CFG_LBC_LSDMR_4;
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asm("sync");
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*sdram_addr = 0xff;
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udelay(100);
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lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation */
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asm("sync");
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*sdram_addr = 0xff;
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udelay(100);
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}
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#else
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void sdram_init(void)
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{
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}
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#endif
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/*
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* The following are used to control the SPI chip selects for the SPI command.
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*/
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#ifdef CONFIG_HARD_SPI
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#define SPI_CS_MASK 0x80000000
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int spi_cs_is_valid(unsigned int bus, unsigned int cs)
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{
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return bus == 0 && cs == 0;
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}
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void spi_cs_activate(struct spi_slave *slave)
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{
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volatile gpio83xx_t *iopd = &((immap_t *)CFG_IMMR)->gpio[0];
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iopd->dat &= ~SPI_CS_MASK;
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}
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void spi_cs_deactivate(struct spi_slave *slave)
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{
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volatile gpio83xx_t *iopd = &((immap_t *)CFG_IMMR)->gpio[0];
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iopd->dat |= SPI_CS_MASK;
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}
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#endif /* CONFIG_HARD_SPI */
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#if defined(CONFIG_OF_BOARD_SETUP)
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void ft_board_setup(void *blob, bd_t *bd)
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{
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ft_cpu_setup(blob, bd);
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#ifdef CONFIG_PCI
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ft_pci_setup(blob, bd);
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#endif
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}
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#endif
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