York Sun 856e4b0d7f powerpc/8xxx: Add additional cycle to write-to-read turnaound for DDR3 ... When DDR data rate is higher than 1200MT/s or controller interleaving is enabled, additional cycle for write-to-read turnaround is needed to satisfy dynamic ODT timing. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>		2011-02-10 23:40:02 -06:00
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ddr	powerpc/8xxx: Add additional cycle to write-to-read turnaound for DDR3	2011-02-10 23:40:02 -06:00
cpu.c	powerpc/p2040: Add various p2040 specific information	2011-01-19 22:58:23 -06:00
fdt.c	powerpc/8xxx: Refactor SRIO initialization into common code	2011-01-14 01:32:21 -06:00
fsl_lbc.c	powerpc/85xx: Add the workaround for erratum ELBC-A001 (enable on P4080)	2011-01-14 01:32:22 -06:00
Makefile	powerpc/8xxx: Refactor SRIO initialization into common code	2011-01-14 01:32:21 -06:00
srio.c	powerpc/8xxx: Refactor SRIO initialization into common code	2011-01-14 01:32:21 -06:00