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https://github.com/brain-hackers/u-boot-brain
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5655108a82
This patch adds basic support for AM33xx which is based on ARMV7 Cortex A8 CPU. Signed-off-by: Chandan Nath <chandan.nath@ti.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
73 lines
1.9 KiB
ArmAsm
73 lines
1.9 KiB
ArmAsm
/*
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* lowlevel_init.S
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*
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* AM33XX low level initialization.
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*
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* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
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*
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* Initial Code by:
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* Mansoor Ahamed <mansoor.ahamed@ti.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <config.h>
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#include <asm/arch/hardware.h>
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_mark1:
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.word mark1
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_lowlevel_init1:
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.word lowlevel_init
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_s_init_start:
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.word s_init_start
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_TEXT_BASE:
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.word CONFIG_SYS_TEXT_BASE /* sdram load addr from config.mk */
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/*****************************************************************************
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* lowlevel_init: - Platform low level init.
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****************************************************************************/
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.globl lowlevel_init
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lowlevel_init:
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/* The link register is saved in ip by start.S */
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mov r6, ip
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/* check if we are already running from RAM */
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ldr r2, _lowlevel_init1
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ldr r3, _TEXT_BASE
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sub r4, r2, r3
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sub r0, pc, r4
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ldr sp, SRAM_STACK
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mark1:
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ldr r5, _mark1
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sub r5, r5, r2 /* bytes between mark1 and lowlevel_init */
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sub r0, r0, r5 /* r0 <- _start w.r.t current place of execution */
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mov r10, #0x0 /* r10 has in_ddr used by s_init() */
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ands r0, r0, #0xC0000000
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/* MSB 2 bits <> 0 then we are in ocmc or DDR */
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cmp r0, #0x80000000
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bne s_init_start
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mov r10, #0x01
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b s_init_start
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s_init_start:
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mov r0, r10 /* passing in_ddr in r0 */
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bl s_init
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/* back to arch calling code */
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mov pc, r6
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/* the literal pools origin */
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.ltorg
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SRAM_STACK:
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/* Place stack at the top */
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.word LOW_LEVEL_SRAM_STACK
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