mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-22 04:30:31 +09:00
84b2cd74f3
So far on Highbank/Midway machines U-Boot only ever uses 512MB of DRAM,
even though the machines have typically 4GB and 8GB, respectively.
That means that so far we didn't need an extra limit for placing the DTB
and initrd, as the 512MB are lower than the kernel's limit ("lowmem",
typically 768MB).
With U-Boot now needing to learn about the actual memory size (to
correctly populate the EFI memory map), it might relocate fdt and initrd
to the end of DRAM, which is out of reach of the kernel.
So add limiting values to the fdt_high and initrd_high environment
variables, to prevent U-Boot from using too high addresses.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
65 lines
1.6 KiB
C
65 lines
1.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2010-2011 Calxeda, Inc.
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#define CONFIG_SYS_BOOTMAPSZ (16 << 20)
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#define CONFIG_SYS_TIMER_RATE (150000000/256)
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#define CONFIG_SYS_TIMER_COUNTER (0xFFF34000 + 0x4)
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#define CONFIG_SYS_TIMER_COUNTS_DOWN
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/*
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* Size of malloc() pool
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*/
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#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
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#define CONFIG_PL011_CLOCK 150000000
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#define CONFIG_PL01x_PORTS { (void *)(0xFFF36000) }
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#define CONFIG_SYS_BOOTCOUNT_LE /* Use little-endian accessors */
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#define CONFIG_SCSI_AHCI_PLAT
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#define CONFIG_SYS_SCSI_MAX_SCSI_ID 5
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#define CONFIG_SYS_SCSI_MAX_LUN 1
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#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
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CONFIG_SYS_SCSI_MAX_LUN)
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#define CONFIG_CALXEDA_XGMAC
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#define CONFIG_BOOT_RETRY_TIME -1
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#define CONFIG_RESET_TO_RETRY
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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#define CONFIG_SYS_LOAD_ADDR 0x800000
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#define CONFIG_SYS_64BIT_LBA
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/*-----------------------------------------------------------------------
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* Physical Memory Map
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* The DRAM is already setup, so do not touch the DT node later.
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*/
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#define PHYS_SDRAM_1_SIZE (4089 << 20)
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/* Environment data setup
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*/
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#define CONFIG_SYS_NVRAM_BASE_ADDR 0xfff88000 /* NVRAM base address */
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#define CONFIG_SYS_NVRAM_SIZE 0x8000 /* NVRAM size */
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#define CONFIG_SYS_SDRAM_BASE 0x00000000
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#define CONFIG_SYS_INIT_SP_ADDR 0x01000000
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#define CONFIG_SKIP_LOWLEVEL_INIT
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"fdt_high=0x20000000\0" \
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"initrd_high=0x20000000\0"
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#endif
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