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https://github.com/brain-hackers/u-boot-brain
synced 2024-08-21 17:38:51 +09:00
![Benoît Thébaudeau](/assets/img/avatar_default.png)
The cache snooping feature of Freescale's eSDHC IP is not available on i.MX, so disable it globally for this architecture. This avoids setting no_snoop for all i.MX boards, and it prevents setting a reserved bit of a reserved register if fsl_esdhc_mmc_init() is used on i.MX, like in arch/arm/cpu/armv7/imx-common/cpu.c/cpu_mmc_init(). Since no_snoop was only used on i.MX, get rid of it BTW. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com> Cc: Andy Fleming <afleming@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Kim Phillips <kim.phillips@freescale.com>
307 lines
8.6 KiB
C
307 lines
8.6 KiB
C
/*
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* (C) Copyright 2011 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/imx-regs.h>
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#include <asm/arch/mx5x_pins.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/arch/iomux.h>
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#include <asm/errno.h>
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#include <netdev.h>
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#include <mmc.h>
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#include <fsl_esdhc.h>
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#include <asm/gpio.h>
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#define ETHERNET_INT IMX_GPIO_NR(2, 31)
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DECLARE_GLOBAL_DATA_PTR;
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int dram_init(void)
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{
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u32 size1, size2;
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size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
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size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
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gd->ram_size = size1 + size2;
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return 0;
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}
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void dram_init_banksize(void)
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{
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gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
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gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
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gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
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gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
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}
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static void setup_iomux_uart(void)
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{
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/* UART1 RXD */
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mxc_request_iomux(MX53_PIN_ATA_DMACK, IOMUX_CONFIG_ALT3);
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mxc_iomux_set_pad(MX53_PIN_ATA_DMACK,
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PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
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PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
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PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
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PAD_CTL_ODE_OPENDRAIN_ENABLE);
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mxc_iomux_set_input(MX53_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, 0x3);
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/* UART1 TXD */
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mxc_request_iomux(MX53_PIN_ATA_DIOW, IOMUX_CONFIG_ALT3);
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mxc_iomux_set_pad(MX53_PIN_ATA_DIOW,
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PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
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PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
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PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
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PAD_CTL_ODE_OPENDRAIN_ENABLE);
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}
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#ifdef CONFIG_FSL_ESDHC
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struct fsl_esdhc_cfg esdhc_cfg[2] = {
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{MMC_SDHC1_BASE_ADDR},
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{MMC_SDHC2_BASE_ADDR},
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};
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int board_mmc_getcd(struct mmc *mmc)
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{
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struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
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int ret;
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mxc_request_iomux(MX53_PIN_GPIO_1, IOMUX_CONFIG_ALT1);
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gpio_direction_input(IMX_GPIO_NR(1, 1));
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mxc_request_iomux(MX53_PIN_GPIO_4, IOMUX_CONFIG_ALT1);
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gpio_direction_input(IMX_GPIO_NR(1, 4));
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if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
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ret = !gpio_get_value(IMX_GPIO_NR(1, 1));
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else
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ret = !gpio_get_value(IMX_GPIO_NR(1, 4));
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return ret;
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}
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int board_mmc_init(bd_t *bis)
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{
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u32 index;
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s32 status = 0;
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for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
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switch (index) {
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case 0:
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mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0);
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mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0);
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mxc_request_iomux(MX53_PIN_SD1_DATA0,
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IOMUX_CONFIG_ALT0);
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mxc_request_iomux(MX53_PIN_SD1_DATA1,
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IOMUX_CONFIG_ALT0);
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mxc_request_iomux(MX53_PIN_SD1_DATA2,
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IOMUX_CONFIG_ALT0);
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mxc_request_iomux(MX53_PIN_SD1_DATA3,
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IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX53_PIN_SD1_CMD, 0x1E4);
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mxc_iomux_set_pad(MX53_PIN_SD1_CLK, 0xD4);
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mxc_iomux_set_pad(MX53_PIN_SD1_DATA0, 0x1D4);
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mxc_iomux_set_pad(MX53_PIN_SD1_DATA1, 0x1D4);
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mxc_iomux_set_pad(MX53_PIN_SD1_DATA2, 0x1D4);
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mxc_iomux_set_pad(MX53_PIN_SD1_DATA3, 0x1D4);
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break;
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case 1:
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mxc_request_iomux(MX53_PIN_SD2_CMD,
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IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
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mxc_request_iomux(MX53_PIN_SD2_CLK,
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IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
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mxc_request_iomux(MX53_PIN_SD2_DATA0,
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IOMUX_CONFIG_ALT0);
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mxc_request_iomux(MX53_PIN_SD2_DATA1,
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IOMUX_CONFIG_ALT0);
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mxc_request_iomux(MX53_PIN_SD2_DATA2,
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IOMUX_CONFIG_ALT0);
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mxc_request_iomux(MX53_PIN_SD2_DATA3,
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IOMUX_CONFIG_ALT0);
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mxc_request_iomux(MX53_PIN_ATA_DATA12,
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IOMUX_CONFIG_ALT2);
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mxc_request_iomux(MX53_PIN_ATA_DATA13,
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IOMUX_CONFIG_ALT2);
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mxc_request_iomux(MX53_PIN_ATA_DATA14,
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IOMUX_CONFIG_ALT2);
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mxc_request_iomux(MX53_PIN_ATA_DATA15,
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IOMUX_CONFIG_ALT2);
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mxc_iomux_set_pad(MX53_PIN_SD2_CMD, 0x1E4);
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mxc_iomux_set_pad(MX53_PIN_SD2_CLK, 0xD4);
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mxc_iomux_set_pad(MX53_PIN_SD2_DATA0, 0x1D4);
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mxc_iomux_set_pad(MX53_PIN_SD2_DATA1, 0x1D4);
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mxc_iomux_set_pad(MX53_PIN_SD2_DATA2, 0x1D4);
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mxc_iomux_set_pad(MX53_PIN_SD2_DATA3, 0x1D4);
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mxc_iomux_set_pad(MX53_PIN_ATA_DATA12, 0x1D4);
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mxc_iomux_set_pad(MX53_PIN_ATA_DATA13, 0x1D4);
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mxc_iomux_set_pad(MX53_PIN_ATA_DATA14, 0x1D4);
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mxc_iomux_set_pad(MX53_PIN_ATA_DATA15, 0x1D4);
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break;
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default:
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printf("Warning: you configured more ESDHC controller"
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"(%d) as supported by the board(2)\n",
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CONFIG_SYS_FSL_ESDHC_NUM);
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return status;
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}
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status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
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}
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return status;
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}
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#endif
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static void weim_smc911x_iomux(void)
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{
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/* ETHERNET_INT as GPIO2_31 */
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mxc_request_iomux(MX53_PIN_EIM_EB3, IOMUX_CONFIG_ALT1);
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gpio_direction_input(ETHERNET_INT);
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/* Data bus */
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mxc_request_iomux(MX53_PIN_EIM_D16, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX53_PIN_EIM_D16, 0xA4);
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mxc_request_iomux(MX53_PIN_EIM_D17, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX53_PIN_EIM_D17, 0xA4);
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mxc_request_iomux(MX53_PIN_EIM_D18, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX53_PIN_EIM_D18, 0xA4);
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mxc_request_iomux(MX53_PIN_EIM_D19, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX53_PIN_EIM_D19, 0xA4);
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mxc_request_iomux(MX53_PIN_EIM_D20, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX53_PIN_EIM_D20, 0xA4);
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mxc_request_iomux(MX53_PIN_EIM_D21, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX53_PIN_EIM_D21, 0xA4);
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mxc_request_iomux(MX53_PIN_EIM_D22, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX53_PIN_EIM_D22, 0xA4);
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mxc_request_iomux(MX53_PIN_EIM_D23, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX53_PIN_EIM_D23, 0xA4);
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mxc_request_iomux(MX53_PIN_EIM_D24, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX53_PIN_EIM_D24, 0xA4);
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mxc_request_iomux(MX53_PIN_EIM_D25, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX53_PIN_EIM_D25, 0xA4);
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mxc_request_iomux(MX53_PIN_EIM_D26, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX53_PIN_EIM_D26, 0xA4);
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mxc_request_iomux(MX53_PIN_EIM_D27, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX53_PIN_EIM_D27, 0xA4);
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mxc_request_iomux(MX53_PIN_EIM_D28, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX53_PIN_EIM_D28, 0xA4);
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mxc_request_iomux(MX53_PIN_EIM_D29, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX53_PIN_EIM_D29, 0xA4);
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mxc_request_iomux(MX53_PIN_EIM_D30, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX53_PIN_EIM_D30, 0xA4);
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mxc_request_iomux(MX53_PIN_EIM_D31, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX53_PIN_EIM_D31, 0xA4);
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/* Address lines */
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mxc_request_iomux(MX53_PIN_EIM_DA0, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX53_PIN_EIM_DA0, 0xA4);
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mxc_request_iomux(MX53_PIN_EIM_DA1, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX53_PIN_EIM_DA1, 0xA4);
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mxc_request_iomux(MX53_PIN_EIM_DA2, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX53_PIN_EIM_DA2, 0xA4);
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mxc_request_iomux(MX53_PIN_EIM_DA3, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX53_PIN_EIM_DA3, 0xA4);
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mxc_request_iomux(MX53_PIN_EIM_DA4, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX53_PIN_EIM_DA4, 0xA4);
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mxc_request_iomux(MX53_PIN_EIM_DA5, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX53_PIN_EIM_DA5, 0xA4);
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mxc_request_iomux(MX53_PIN_EIM_DA6, IOMUX_CONFIG_ALT0);
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mxc_iomux_set_pad(MX53_PIN_EIM_DA6, 0xA4);
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/* other EIM signals for ethernet */
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mxc_request_iomux(MX53_PIN_EIM_OE, IOMUX_CONFIG_ALT0);
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mxc_request_iomux(MX53_PIN_EIM_RW, IOMUX_CONFIG_ALT0);
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mxc_request_iomux(MX53_PIN_EIM_CS1, IOMUX_CONFIG_ALT0);
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}
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static void weim_cs1_settings(void)
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{
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struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR;
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writel(MX53ARD_CS1GCR1, &weim_regs->cs1gcr1);
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writel(0x0, &weim_regs->cs1gcr2);
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writel(MX53ARD_CS1RCR1, &weim_regs->cs1rcr1);
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writel(MX53ARD_CS1RCR2, &weim_regs->cs1rcr2);
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writel(MX53ARD_CS1WCR1, &weim_regs->cs1wcr1);
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writel(0x0, &weim_regs->cs1wcr2);
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writel(0x0, &weim_regs->wcr);
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set_chipselect_size(CS0_64M_CS1_64M);
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}
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int board_early_init_f(void)
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{
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setup_iomux_uart();
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return 0;
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}
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int board_init(void)
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{
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/* address of boot parameters */
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gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
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return 0;
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}
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int board_eth_init(bd_t *bis)
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{
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int rc = -ENODEV;
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weim_smc911x_iomux();
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weim_cs1_settings();
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#ifdef CONFIG_SMC911X
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rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
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#endif
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return rc;
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}
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int checkboard(void)
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{
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puts("Board: MX53ARD\n");
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return 0;
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}
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