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![Aneesh V](/assets/img/avatar_default.png)
1. make sure that page table setup is not done multiple times 2. flush_dcache_all() is more appropriate while disabling cache than a range flush on the entire memory(flush_cache()) Provide a default implementation for flush_dcache_all() for backward compatibility and to avoid build issues. Signed-off-by: Aneesh V <aneesh@ti.com>
196 lines
3.9 KiB
C
196 lines
3.9 KiB
C
/*
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* (C) Copyright 2002
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/system.h>
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#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
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#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH)
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#define CACHE_SETUP 0x1a
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#else
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#define CACHE_SETUP 0x1e
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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void __arm_init_before_mmu(void)
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{
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}
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void arm_init_before_mmu(void)
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__attribute__((weak, alias("__arm_init_before_mmu")));
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static void cp_delay (void)
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{
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volatile int i;
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/* copro seems to need some delay between reading and writing */
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for (i = 0; i < 100; i++)
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nop();
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asm volatile("" : : : "memory");
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}
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static inline void dram_bank_mmu_setup(int bank)
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{
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u32 *page_table = (u32 *)gd->tlb_addr;
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bd_t *bd = gd->bd;
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int i;
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debug("%s: bank: %d\n", __func__, bank);
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for (i = bd->bi_dram[bank].start >> 20;
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i < (bd->bi_dram[bank].start + bd->bi_dram[bank].size) >> 20;
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i++) {
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page_table[i] = i << 20 | (3 << 10) | CACHE_SETUP;
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}
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}
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/* to activate the MMU we need to set up virtual memory: use 1M areas */
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static inline void mmu_setup(void)
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{
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u32 *page_table = (u32 *)gd->tlb_addr;
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int i;
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u32 reg;
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arm_init_before_mmu();
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/* Set up an identity-mapping for all 4GB, rw for everyone */
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for (i = 0; i < 4096; i++)
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page_table[i] = i << 20 | (3 << 10) | 0x12;
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for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
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dram_bank_mmu_setup(i);
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}
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/* Copy the page table address to cp15 */
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asm volatile("mcr p15, 0, %0, c2, c0, 0"
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: : "r" (page_table) : "memory");
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/* Set the access control to all-supervisor */
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asm volatile("mcr p15, 0, %0, c3, c0, 0"
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: : "r" (~0));
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/* and enable the mmu */
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reg = get_cr(); /* get control reg. */
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cp_delay();
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set_cr(reg | CR_M);
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}
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static int mmu_enabled(void)
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{
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return get_cr() & CR_M;
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}
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/* cache_bit must be either CR_I or CR_C */
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static void cache_enable(uint32_t cache_bit)
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{
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uint32_t reg;
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/* The data cache is not active unless the mmu is enabled too */
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if ((cache_bit == CR_C) && !mmu_enabled())
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mmu_setup();
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reg = get_cr(); /* get control reg. */
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cp_delay();
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set_cr(reg | cache_bit);
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}
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/* cache_bit must be either CR_I or CR_C */
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static void cache_disable(uint32_t cache_bit)
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{
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uint32_t reg;
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if (cache_bit == CR_C) {
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/* if cache isn;t enabled no need to disable */
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reg = get_cr();
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if ((reg & CR_C) != CR_C)
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return;
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/* if disabling data cache, disable mmu too */
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cache_bit |= CR_M;
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flush_dcache_all();
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}
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reg = get_cr();
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cp_delay();
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set_cr(reg & ~cache_bit);
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}
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#endif
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#ifdef CONFIG_SYS_ICACHE_OFF
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void icache_enable (void)
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{
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return;
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}
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void icache_disable (void)
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{
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return;
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}
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int icache_status (void)
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{
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return 0; /* always off */
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}
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#else
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void icache_enable(void)
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{
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cache_enable(CR_I);
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}
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void icache_disable(void)
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{
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cache_disable(CR_I);
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}
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int icache_status(void)
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{
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return (get_cr() & CR_I) != 0;
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}
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#endif
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#ifdef CONFIG_SYS_DCACHE_OFF
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void dcache_enable (void)
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{
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return;
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}
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void dcache_disable (void)
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{
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return;
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}
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int dcache_status (void)
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{
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return 0; /* always off */
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}
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#else
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void dcache_enable(void)
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{
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cache_enable(CR_C);
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}
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void dcache_disable(void)
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{
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cache_disable(CR_C);
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}
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int dcache_status(void)
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{
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return (get_cr() & CR_C) != 0;
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}
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#endif
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