mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-10 05:06:16 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
251 lines
7.3 KiB
C
251 lines
7.3 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2008,2010 Freescale Semiconductor, Inc.
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* Dave Liu <daveliu@freescale.com>
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*/
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#include <config.h>
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#include <common.h>
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#include <asm/io.h>
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#include <asm/immap_85xx.h>
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#include <asm/fsl_serdes.h>
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/* PORDEVSR register */
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#define GUTS_PORDEVSR_OFFS 0xc
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#define GUTS_PORDEVSR_SERDES2_IO_SEL 0x38000000
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#define GUTS_PORDEVSR_SERDES2_IO_SEL_SHIFT 27
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/* SerDes CR0 register */
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#define FSL_SRDSCR0_OFFS 0x0
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#define FSL_SRDSCR0_TXEQA_MASK 0x00007000
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#define FSL_SRDSCR0_TXEQA_SGMII 0x00004000
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#define FSL_SRDSCR0_TXEQA_SATA 0x00001000
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#define FSL_SRDSCR0_TXEQE_MASK 0x00000700
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#define FSL_SRDSCR0_TXEQE_SGMII 0x00000400
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#define FSL_SRDSCR0_TXEQE_SATA 0x00000100
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/* SerDes CR1 register */
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#define FSL_SRDSCR1_OFFS 0x4
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#define FSL_SRDSCR1_LANEA_MASK 0x80200000
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#define FSL_SRDSCR1_LANEA_OFF 0x80200000
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#define FSL_SRDSCR1_LANEE_MASK 0x08020000
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#define FSL_SRDSCR1_LANEE_OFF 0x08020000
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/* SerDes CR2 register */
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#define FSL_SRDSCR2_OFFS 0x8
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#define FSL_SRDSCR2_EICA_MASK 0x00001f00
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#define FSL_SRDSCR2_EICA_SGMII 0x00000400
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#define FSL_SRDSCR2_EICA_SATA 0x00001400
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#define FSL_SRDSCR2_EICE_MASK 0x0000001f
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#define FSL_SRDSCR2_EICE_SGMII 0x00000004
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#define FSL_SRDSCR2_EICE_SATA 0x00000014
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/* SerDes CR3 register */
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#define FSL_SRDSCR3_OFFS 0xc
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#define FSL_SRDSCR3_LANEA_MASK 0x3f000700
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#define FSL_SRDSCR3_LANEA_SGMII 0x00000000
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#define FSL_SRDSCR3_LANEA_SATA 0x15000500
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#define FSL_SRDSCR3_LANEE_MASK 0x003f0007
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#define FSL_SRDSCR3_LANEE_SGMII 0x00000000
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#define FSL_SRDSCR3_LANEE_SATA 0x00150005
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#define SRDS1_MAX_LANES 8
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#define SRDS2_MAX_LANES 2
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static u32 serdes1_prtcl_map, serdes2_prtcl_map;
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static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
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[0x2] = {PCIE1, PCIE1, PCIE1, PCIE1, NONE, NONE, NONE, NONE},
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[0x3] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1, PCIE1},
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[0x5] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE2, PCIE2},
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[0x7] = {PCIE1, PCIE1, PCIE1, PCIE1, PCIE2, PCIE2, PCIE3, PCIE3},
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};
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static u8 serdes2_cfg_tbl[][SRDS2_MAX_LANES] = {
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[0x1] = {SATA1, SATA2},
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[0x3] = {SATA1, NONE},
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[0x4] = {SGMII_TSEC1, SGMII_TSEC3},
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[0x6] = {SGMII_TSEC1, NONE},
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};
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int is_serdes_configured(enum srds_prtcl device)
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{
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int ret;
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if (!(serdes1_prtcl_map & (1 << NONE)))
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fsl_serdes_init();
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ret = (1 << device) & serdes1_prtcl_map;
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if (ret)
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return ret;
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if (!(serdes2_prtcl_map & (1 << NONE)))
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fsl_serdes_init();
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return (1 << device) & serdes2_prtcl_map;
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}
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void fsl_serdes_init(void)
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{
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void *guts = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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void *sd = (void *)CONFIG_SYS_MPC85xx_SERDES2_ADDR;
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u32 pordevsr = in_be32(guts + GUTS_PORDEVSR_OFFS);
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u32 srds1_io_sel, srds2_io_sel;
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u32 tmp;
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int lane;
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if (serdes1_prtcl_map & (1 << NONE) &&
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serdes2_prtcl_map & (1 << NONE))
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return;
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srds1_io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
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MPC85xx_PORDEVSR_IO_SEL_SHIFT;
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/* parse the SRDS2_IO_SEL of PORDEVSR */
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srds2_io_sel = (pordevsr & GUTS_PORDEVSR_SERDES2_IO_SEL)
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>> GUTS_PORDEVSR_SERDES2_IO_SEL_SHIFT;
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debug("PORDEVSR[SRDS1_IO_SEL] = %x\n", srds1_io_sel);
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debug("PORDEVSR[SRDS2_IO_SEL] = %x\n", srds2_io_sel);
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switch (srds2_io_sel) {
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case 1: /* Lane A - SATA1, Lane E - SATA2 */
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/* CR 0 */
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tmp = in_be32(sd + FSL_SRDSCR0_OFFS);
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tmp &= ~FSL_SRDSCR0_TXEQA_MASK;
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tmp |= FSL_SRDSCR0_TXEQA_SATA;
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tmp &= ~FSL_SRDSCR0_TXEQE_MASK;
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tmp |= FSL_SRDSCR0_TXEQE_SATA;
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out_be32(sd + FSL_SRDSCR0_OFFS, tmp);
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/* CR 1 */
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tmp = in_be32(sd + FSL_SRDSCR1_OFFS);
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tmp &= ~FSL_SRDSCR1_LANEA_MASK;
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tmp &= ~FSL_SRDSCR1_LANEE_MASK;
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out_be32(sd + FSL_SRDSCR1_OFFS, tmp);
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/* CR 2 */
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tmp = in_be32(sd + FSL_SRDSCR2_OFFS);
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tmp &= ~FSL_SRDSCR2_EICA_MASK;
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tmp |= FSL_SRDSCR2_EICA_SATA;
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tmp &= ~FSL_SRDSCR2_EICE_MASK;
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tmp |= FSL_SRDSCR2_EICE_SATA;
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out_be32(sd + FSL_SRDSCR2_OFFS, tmp);
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/* CR 3 */
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tmp = in_be32(sd + FSL_SRDSCR3_OFFS);
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tmp &= ~FSL_SRDSCR3_LANEA_MASK;
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tmp |= FSL_SRDSCR3_LANEA_SATA;
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tmp &= ~FSL_SRDSCR3_LANEE_MASK;
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tmp |= FSL_SRDSCR3_LANEE_SATA;
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out_be32(sd + FSL_SRDSCR3_OFFS, tmp);
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break;
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case 3: /* Lane A - SATA1, Lane E - disabled */
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/* CR 0 */
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tmp = in_be32(sd + FSL_SRDSCR0_OFFS);
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tmp &= ~FSL_SRDSCR0_TXEQA_MASK;
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tmp |= FSL_SRDSCR0_TXEQA_SATA;
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out_be32(sd + FSL_SRDSCR0_OFFS, tmp);
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/* CR 1 */
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tmp = in_be32(sd + FSL_SRDSCR1_OFFS);
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tmp &= ~FSL_SRDSCR1_LANEE_MASK;
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tmp |= FSL_SRDSCR1_LANEE_OFF;
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out_be32(sd + FSL_SRDSCR1_OFFS, tmp);
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/* CR 2 */
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tmp = in_be32(sd + FSL_SRDSCR2_OFFS);
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tmp &= ~FSL_SRDSCR2_EICA_MASK;
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tmp |= FSL_SRDSCR2_EICA_SATA;
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out_be32(sd + FSL_SRDSCR2_OFFS, tmp);
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/* CR 3 */
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tmp = in_be32(sd + FSL_SRDSCR3_OFFS);
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tmp &= ~FSL_SRDSCR3_LANEA_MASK;
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tmp |= FSL_SRDSCR3_LANEA_SATA;
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out_be32(sd + FSL_SRDSCR3_OFFS, tmp);
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break;
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case 4: /* Lane A - eTSEC1 SGMII, Lane E - eTSEC3 SGMII */
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/* CR 0 */
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tmp = in_be32(sd + FSL_SRDSCR0_OFFS);
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tmp &= ~FSL_SRDSCR0_TXEQA_MASK;
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tmp |= FSL_SRDSCR0_TXEQA_SGMII;
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tmp &= ~FSL_SRDSCR0_TXEQE_MASK;
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tmp |= FSL_SRDSCR0_TXEQE_SGMII;
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out_be32(sd + FSL_SRDSCR0_OFFS, tmp);
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/* CR 1 */
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tmp = in_be32(sd + FSL_SRDSCR1_OFFS);
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tmp &= ~FSL_SRDSCR1_LANEA_MASK;
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tmp &= ~FSL_SRDSCR1_LANEE_MASK;
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out_be32(sd + FSL_SRDSCR1_OFFS, tmp);
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/* CR 2 */
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tmp = in_be32(sd + FSL_SRDSCR2_OFFS);
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tmp &= ~FSL_SRDSCR2_EICA_MASK;
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tmp |= FSL_SRDSCR2_EICA_SGMII;
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tmp &= ~FSL_SRDSCR2_EICE_MASK;
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tmp |= FSL_SRDSCR2_EICE_SGMII;
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out_be32(sd + FSL_SRDSCR2_OFFS, tmp);
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/* CR 3 */
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tmp = in_be32(sd + FSL_SRDSCR3_OFFS);
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tmp &= ~FSL_SRDSCR3_LANEA_MASK;
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tmp |= FSL_SRDSCR3_LANEA_SGMII;
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tmp &= ~FSL_SRDSCR3_LANEE_MASK;
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tmp |= FSL_SRDSCR3_LANEE_SGMII;
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out_be32(sd + FSL_SRDSCR3_OFFS, tmp);
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break;
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case 6: /* Lane A - eTSEC1 SGMII, Lane E - disabled */
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/* CR 0 */
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tmp = in_be32(sd + FSL_SRDSCR0_OFFS);
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tmp &= ~FSL_SRDSCR0_TXEQA_MASK;
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tmp |= FSL_SRDSCR0_TXEQA_SGMII;
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out_be32(sd + FSL_SRDSCR0_OFFS, tmp);
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/* CR 1 */
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tmp = in_be32(sd + FSL_SRDSCR1_OFFS);
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tmp &= ~FSL_SRDSCR1_LANEE_MASK;
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tmp |= FSL_SRDSCR1_LANEE_OFF;
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out_be32(sd + FSL_SRDSCR1_OFFS, tmp);
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/* CR 2 */
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tmp = in_be32(sd + FSL_SRDSCR2_OFFS);
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tmp &= ~FSL_SRDSCR2_EICA_MASK;
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tmp |= FSL_SRDSCR2_EICA_SGMII;
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out_be32(sd + FSL_SRDSCR2_OFFS, tmp);
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/* CR 3 */
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tmp = in_be32(sd + FSL_SRDSCR3_OFFS);
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tmp &= ~FSL_SRDSCR3_LANEA_MASK;
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tmp |= FSL_SRDSCR3_LANEA_SGMII;
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out_be32(sd + FSL_SRDSCR3_OFFS, tmp);
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break;
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case 7: /* Lane A - disabled, Lane E - disabled */
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/* CR 1 */
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tmp = in_be32(sd + FSL_SRDSCR1_OFFS);
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tmp &= ~FSL_SRDSCR1_LANEA_MASK;
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tmp |= FSL_SRDSCR1_LANEA_OFF;
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tmp &= ~FSL_SRDSCR1_LANEE_MASK;
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tmp |= FSL_SRDSCR1_LANEE_OFF;
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out_be32(sd + FSL_SRDSCR1_OFFS, tmp);
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break;
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default:
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break;
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}
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if (srds1_io_sel >= ARRAY_SIZE(serdes1_cfg_tbl)) {
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printf("Invalid PORDEVSR[SRDS1_IO_SEL] = %d\n", srds1_io_sel);
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return;
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}
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for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
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enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds1_io_sel][lane];
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serdes1_prtcl_map |= (1 << lane_prtcl);
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}
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/* Set the first bit to indicate serdes has been initialized */
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serdes1_prtcl_map |= (1 << NONE);
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if (srds2_io_sel >= ARRAY_SIZE(serdes2_cfg_tbl)) {
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printf("Invalid PORDEVSR[SRDS2_IO_SEL] = %d\n", srds2_io_sel);
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return;
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}
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for (lane = 0; lane < SRDS2_MAX_LANES; lane++) {
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enum srds_prtcl lane_prtcl = serdes2_cfg_tbl[srds2_io_sel][lane];
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serdes2_prtcl_map |= (1 << lane_prtcl);
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}
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/* Set the first bit to indicate serdes has been initialized */
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serdes2_prtcl_map |= (1 << NONE);
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}
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