mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-07 19:56:18 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
383 lines
10 KiB
C
383 lines
10 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2016-2017 Intel Corporation
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*/
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#include <asm/io.h>
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#include <asm/arch/fpga_manager.h>
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#include <asm/arch/misc.h>
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#include <asm/arch/reset_manager.h>
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#include <asm/arch/system_manager.h>
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#include <common.h>
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#include <errno.h>
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#include <fdtdec.h>
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#include <wait_bit.h>
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DECLARE_GLOBAL_DATA_PTR;
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static const struct socfpga_reset_manager *reset_manager_base =
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(void *)SOCFPGA_RSTMGR_ADDRESS;
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static const struct socfpga_system_manager *sysmgr_regs =
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(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
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#define ECC_MASK (ALT_RSTMGR_PER0MODRST_EMACECC0_SET_MSK | \
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ALT_RSTMGR_PER0MODRST_EMACECC1_SET_MSK | \
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ALT_RSTMGR_PER0MODRST_EMACECC2_SET_MSK | \
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ALT_RSTMGR_PER0MODRST_NANDECC_SET_MSK | \
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ALT_RSTMGR_PER0MODRST_QSPIECC_SET_MSK | \
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ALT_RSTMGR_PER0MODRST_SDMMCECC_SET_MSK)
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void socfpga_reset_uart(int assert)
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{
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unsigned int com_port;
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com_port = uart_com_port(gd->fdt_blob);
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if (com_port == SOCFPGA_UART1_ADDRESS)
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socfpga_per_reset(SOCFPGA_RESET(UART1), assert);
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else if (com_port == SOCFPGA_UART0_ADDRESS)
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socfpga_per_reset(SOCFPGA_RESET(UART0), assert);
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}
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static const u32 per0fpgamasks[] = {
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ALT_RSTMGR_PER0MODRST_EMACECC0_SET_MSK |
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ALT_RSTMGR_PER0MODRST_EMAC0_SET_MSK,
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ALT_RSTMGR_PER0MODRST_EMACECC1_SET_MSK |
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ALT_RSTMGR_PER0MODRST_EMAC1_SET_MSK,
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ALT_RSTMGR_PER0MODRST_EMACECC2_SET_MSK |
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ALT_RSTMGR_PER0MODRST_EMAC2_SET_MSK,
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0, /* i2c0 per1mod */
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0, /* i2c1 per1mod */
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0, /* i2c0_emac */
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0, /* i2c1_emac */
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0, /* i2c2_emac */
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ALT_RSTMGR_PER0MODRST_NANDECC_SET_MSK |
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ALT_RSTMGR_PER0MODRST_NAND_SET_MSK,
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ALT_RSTMGR_PER0MODRST_QSPIECC_SET_MSK |
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ALT_RSTMGR_PER0MODRST_QSPI_SET_MSK,
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ALT_RSTMGR_PER0MODRST_SDMMCECC_SET_MSK |
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ALT_RSTMGR_PER0MODRST_SDMMC_SET_MSK,
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ALT_RSTMGR_PER0MODRST_SPIM0_SET_MSK,
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ALT_RSTMGR_PER0MODRST_SPIM1_SET_MSK,
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ALT_RSTMGR_PER0MODRST_SPIS0_SET_MSK,
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ALT_RSTMGR_PER0MODRST_SPIS1_SET_MSK,
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0, /* uart0 per1mod */
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0, /* uart1 per1mod */
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};
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static const u32 per1fpgamasks[] = {
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0, /* emac0 per0mod */
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0, /* emac1 per0mod */
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0, /* emac2 per0mod */
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ALT_RSTMGR_PER1MODRST_I2C0_SET_MSK,
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ALT_RSTMGR_PER1MODRST_I2C1_SET_MSK,
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ALT_RSTMGR_PER1MODRST_I2C2_SET_MSK, /* i2c0_emac */
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ALT_RSTMGR_PER1MODRST_I2C3_SET_MSK, /* i2c1_emac */
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ALT_RSTMGR_PER1MODRST_I2C4_SET_MSK, /* i2c2_emac */
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0, /* nand per0mod */
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0, /* qspi per0mod */
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0, /* sdmmc per0mod */
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0, /* spim0 per0mod */
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0, /* spim1 per0mod */
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0, /* spis0 per0mod */
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0, /* spis1 per0mod */
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ALT_RSTMGR_PER1MODRST_UART0_SET_MSK,
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ALT_RSTMGR_PER1MODRST_UART1_SET_MSK,
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};
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struct bridge_cfg {
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int compat_id;
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u32 mask_noc;
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u32 mask_rstmgr;
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};
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static const struct bridge_cfg bridge_cfg_tbl[] = {
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{
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COMPAT_ALTERA_SOCFPGA_H2F_BRG,
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ALT_SYSMGR_NOC_H2F_SET_MSK,
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ALT_RSTMGR_BRGMODRST_H2F_SET_MSK,
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},
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{
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COMPAT_ALTERA_SOCFPGA_LWH2F_BRG,
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ALT_SYSMGR_NOC_LWH2F_SET_MSK,
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ALT_RSTMGR_BRGMODRST_LWH2F_SET_MSK,
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},
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{
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COMPAT_ALTERA_SOCFPGA_F2H_BRG,
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ALT_SYSMGR_NOC_F2H_SET_MSK,
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ALT_RSTMGR_BRGMODRST_F2H_SET_MSK,
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},
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{
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COMPAT_ALTERA_SOCFPGA_F2SDR0,
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ALT_SYSMGR_NOC_F2SDR0_SET_MSK,
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ALT_RSTMGR_BRGMODRST_F2SSDRAM0_SET_MSK,
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},
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{
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COMPAT_ALTERA_SOCFPGA_F2SDR1,
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ALT_SYSMGR_NOC_F2SDR1_SET_MSK,
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ALT_RSTMGR_BRGMODRST_F2SSDRAM1_SET_MSK,
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},
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{
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COMPAT_ALTERA_SOCFPGA_F2SDR2,
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ALT_SYSMGR_NOC_F2SDR2_SET_MSK,
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ALT_RSTMGR_BRGMODRST_F2SSDRAM2_SET_MSK,
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},
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};
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/* Disable the watchdog (toggle reset to watchdog) */
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void socfpga_watchdog_disable(void)
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{
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/* assert reset for watchdog */
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setbits_le32(&reset_manager_base->per1modrst,
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ALT_RSTMGR_PER1MODRST_WD0_SET_MSK);
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}
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/* Release NOC ddr scheduler from reset */
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void socfpga_reset_deassert_noc_ddr_scheduler(void)
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{
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clrbits_le32(&reset_manager_base->brgmodrst,
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ALT_RSTMGR_BRGMODRST_DDRSCH_SET_MSK);
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}
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/* Check whether Watchdog in reset state? */
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int socfpga_is_wdt_in_reset(void)
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{
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u32 val;
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val = readl(&reset_manager_base->per1modrst);
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val &= ALT_RSTMGR_PER1MODRST_WD0_SET_MSK;
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/* return 0x1 if watchdog in reset */
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return val;
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}
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/* emacbase: base address of emac to enable/disable reset
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* state: 0 - disable reset, !0 - enable reset
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*/
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void socfpga_emac_manage_reset(ulong emacbase, u32 state)
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{
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ulong eccmask;
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ulong emacmask;
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switch (emacbase) {
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case SOCFPGA_EMAC0_ADDRESS:
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eccmask = ALT_RSTMGR_PER0MODRST_EMACECC0_SET_MSK;
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emacmask = ALT_RSTMGR_PER0MODRST_EMAC0_SET_MSK;
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break;
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case SOCFPGA_EMAC1_ADDRESS:
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eccmask = ALT_RSTMGR_PER0MODRST_EMACECC1_SET_MSK;
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emacmask = ALT_RSTMGR_PER0MODRST_EMAC1_SET_MSK;
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break;
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case SOCFPGA_EMAC2_ADDRESS:
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eccmask = ALT_RSTMGR_PER0MODRST_EMACECC2_SET_MSK;
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emacmask = ALT_RSTMGR_PER0MODRST_EMAC2_SET_MSK;
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break;
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default:
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pr_err("emac base address unexpected! %lx", emacbase);
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hang();
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break;
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}
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if (state) {
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/* Enable ECC OCP first */
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setbits_le32(&reset_manager_base->per0modrst, eccmask);
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setbits_le32(&reset_manager_base->per0modrst, emacmask);
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} else {
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/* Disable ECC OCP first */
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clrbits_le32(&reset_manager_base->per0modrst, emacmask);
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clrbits_le32(&reset_manager_base->per0modrst, eccmask);
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}
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}
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static int get_bridge_init_val(const void *blob, int compat_id)
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{
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int node;
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node = fdtdec_next_compatible(blob, 0, compat_id);
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if (node < 0)
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return 0;
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return fdtdec_get_uint(blob, node, "init-val", 0);
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}
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/* Enable bridges (hps2fpga, lwhps2fpga, fpga2hps, fpga2sdram) per handoff */
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int socfpga_reset_deassert_bridges_handoff(void)
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{
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u32 mask_noc = 0, mask_rstmgr = 0;
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int i;
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for (i = 0; i < ARRAY_SIZE(bridge_cfg_tbl); i++) {
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if (get_bridge_init_val(gd->fdt_blob,
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bridge_cfg_tbl[i].compat_id)) {
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mask_noc |= bridge_cfg_tbl[i].mask_noc;
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mask_rstmgr |= bridge_cfg_tbl[i].mask_rstmgr;
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}
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}
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/* clear idle request to all bridges */
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setbits_le32(&sysmgr_regs->noc_idlereq_clr, mask_noc);
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/* Release bridges from reset state per handoff value */
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clrbits_le32(&reset_manager_base->brgmodrst, mask_rstmgr);
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/* Poll until all idleack to 0, timeout at 1000ms */
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return wait_for_bit_le32(&sysmgr_regs->noc_idleack, mask_noc,
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false, 1000, false);
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}
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void socfpga_reset_assert_fpga_connected_peripherals(void)
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{
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u32 mask0 = 0;
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u32 mask1 = 0;
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u32 fpga_pinux_addr = SOCFPGA_PINMUX_FPGA_INTERFACE_ADDRESS;
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int i;
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for (i = 0; i < ARRAY_SIZE(per1fpgamasks); i++) {
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if (readl(fpga_pinux_addr)) {
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mask0 |= per0fpgamasks[i];
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mask1 |= per1fpgamasks[i];
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}
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fpga_pinux_addr += sizeof(u32);
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}
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setbits_le32(&reset_manager_base->per0modrst, mask0 & ECC_MASK);
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setbits_le32(&reset_manager_base->per1modrst, mask1);
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setbits_le32(&reset_manager_base->per0modrst, mask0);
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}
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/* Release L4 OSC1 Watchdog Timer 0 from reset through reset manager */
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void socfpga_reset_deassert_osc1wd0(void)
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{
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clrbits_le32(&reset_manager_base->per1modrst,
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ALT_RSTMGR_PER1MODRST_WD0_SET_MSK);
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}
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/*
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* Assert or de-assert SoCFPGA reset manager reset.
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*/
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void socfpga_per_reset(u32 reset, int set)
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{
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const u32 *reg;
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u32 rstmgr_bank = RSTMGR_BANK(reset);
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switch (rstmgr_bank) {
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case 0:
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reg = &reset_manager_base->mpumodrst;
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break;
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case 1:
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reg = &reset_manager_base->per0modrst;
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break;
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case 2:
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reg = &reset_manager_base->per1modrst;
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break;
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case 3:
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reg = &reset_manager_base->brgmodrst;
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break;
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case 4:
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reg = &reset_manager_base->sysmodrst;
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break;
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default:
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return;
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}
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if (set)
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setbits_le32(reg, 1 << RSTMGR_RESET(reset));
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else
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clrbits_le32(reg, 1 << RSTMGR_RESET(reset));
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}
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/*
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* Assert reset on every peripheral but L4WD0.
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* Watchdog must be kept intact to prevent glitches
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* and/or hangs.
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* For the Arria10, we disable all the peripherals except L4 watchdog0,
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* L4 Timer 0, and ECC.
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*/
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void socfpga_per_reset_all(void)
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{
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const u32 l4wd0 = (1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0)) |
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(1 << RSTMGR_RESET(SOCFPGA_RESET(L4SYSTIMER0))));
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unsigned mask_ecc_ocp =
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ALT_RSTMGR_PER0MODRST_EMACECC0_SET_MSK |
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ALT_RSTMGR_PER0MODRST_EMACECC1_SET_MSK |
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ALT_RSTMGR_PER0MODRST_EMACECC2_SET_MSK |
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ALT_RSTMGR_PER0MODRST_USBECC0_SET_MSK |
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ALT_RSTMGR_PER0MODRST_USBECC1_SET_MSK |
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ALT_RSTMGR_PER0MODRST_NANDECC_SET_MSK |
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ALT_RSTMGR_PER0MODRST_QSPIECC_SET_MSK |
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ALT_RSTMGR_PER0MODRST_SDMMCECC_SET_MSK;
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/* disable all components except ECC_OCP, L4 Timer0 and L4 WD0 */
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writel(~l4wd0, &reset_manager_base->per1modrst);
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setbits_le32(&reset_manager_base->per0modrst, ~mask_ecc_ocp);
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/* Finally disable the ECC_OCP */
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setbits_le32(&reset_manager_base->per0modrst, mask_ecc_ocp);
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}
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#if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
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int socfpga_bridges_reset(void)
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{
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/* For SoCFPGA-VT, this is NOP. */
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return 0;
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}
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#else
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int socfpga_bridges_reset(void)
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{
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int ret;
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/* Disable all the bridges (hps2fpga, lwhps2fpga, fpga2hps,
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fpga2sdram) */
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/* set idle request to all bridges */
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writel(ALT_SYSMGR_NOC_H2F_SET_MSK |
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ALT_SYSMGR_NOC_LWH2F_SET_MSK |
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ALT_SYSMGR_NOC_F2H_SET_MSK |
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ALT_SYSMGR_NOC_F2SDR0_SET_MSK |
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ALT_SYSMGR_NOC_F2SDR1_SET_MSK |
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ALT_SYSMGR_NOC_F2SDR2_SET_MSK,
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&sysmgr_regs->noc_idlereq_set);
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/* Enable the NOC timeout */
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writel(ALT_SYSMGR_NOC_TMO_EN_SET_MSK, &sysmgr_regs->noc_timeout);
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/* Poll until all idleack to 1 */
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ret = wait_for_bit_le32(&sysmgr_regs->noc_idleack,
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ALT_SYSMGR_NOC_H2F_SET_MSK |
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ALT_SYSMGR_NOC_LWH2F_SET_MSK |
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ALT_SYSMGR_NOC_F2H_SET_MSK |
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ALT_SYSMGR_NOC_F2SDR0_SET_MSK |
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ALT_SYSMGR_NOC_F2SDR1_SET_MSK |
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ALT_SYSMGR_NOC_F2SDR2_SET_MSK,
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true, 10000, false);
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if (ret)
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return ret;
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/* Poll until all idlestatus to 1 */
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ret = wait_for_bit_le32(&sysmgr_regs->noc_idlestatus,
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ALT_SYSMGR_NOC_H2F_SET_MSK |
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ALT_SYSMGR_NOC_LWH2F_SET_MSK |
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ALT_SYSMGR_NOC_F2H_SET_MSK |
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ALT_SYSMGR_NOC_F2SDR0_SET_MSK |
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ALT_SYSMGR_NOC_F2SDR1_SET_MSK |
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ALT_SYSMGR_NOC_F2SDR2_SET_MSK,
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true, 10000, false);
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if (ret)
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return ret;
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/* Put all bridges (except NOR DDR scheduler) into reset state */
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setbits_le32(&reset_manager_base->brgmodrst,
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(ALT_RSTMGR_BRGMODRST_H2F_SET_MSK |
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ALT_RSTMGR_BRGMODRST_LWH2F_SET_MSK |
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ALT_RSTMGR_BRGMODRST_F2H_SET_MSK |
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ALT_RSTMGR_BRGMODRST_F2SSDRAM0_SET_MSK |
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ALT_RSTMGR_BRGMODRST_F2SSDRAM1_SET_MSK |
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ALT_RSTMGR_BRGMODRST_F2SSDRAM2_SET_MSK));
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/* Disable NOC timeout */
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writel(0, &sysmgr_regs->noc_timeout);
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return 0;
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}
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#endif
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