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https://github.com/brain-hackers/u-boot-brain
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![Tom Rini](/assets/img/avatar_default.png)
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
359 lines
8.2 KiB
C
359 lines
8.2 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2017, STMicroelectronics - All Rights Reserved
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* Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
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*/
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#include <common.h>
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#include <errno.h>
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#include <asm/armv7m.h>
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#include <asm/io.h>
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/* Cache maintenance operation registers */
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#define V7M_CACHE_REG_ICIALLU ((u32 *)(V7M_CACHE_MAINT_BASE + 0x00))
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#define INVAL_ICACHE_POU 0
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#define V7M_CACHE_REG_ICIMVALU ((u32 *)(V7M_CACHE_MAINT_BASE + 0x08))
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#define V7M_CACHE_REG_DCIMVAC ((u32 *)(V7M_CACHE_MAINT_BASE + 0x0C))
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#define V7M_CACHE_REG_DCISW ((u32 *)(V7M_CACHE_MAINT_BASE + 0x10))
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#define V7M_CACHE_REG_DCCMVAU ((u32 *)(V7M_CACHE_MAINT_BASE + 0x14))
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#define V7M_CACHE_REG_DCCMVAC ((u32 *)(V7M_CACHE_MAINT_BASE + 0x18))
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#define V7M_CACHE_REG_DCCSW ((u32 *)(V7M_CACHE_MAINT_BASE + 0x1C))
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#define V7M_CACHE_REG_DCCIMVAC ((u32 *)(V7M_CACHE_MAINT_BASE + 0x20))
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#define V7M_CACHE_REG_DCCISW ((u32 *)(V7M_CACHE_MAINT_BASE + 0x24))
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#define WAYS_SHIFT 30
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#define SETS_SHIFT 5
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/* armv7m processor feature registers */
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#define V7M_PROC_REG_CLIDR ((u32 *)(V7M_PROC_FTR_BASE + 0x00))
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#define V7M_PROC_REG_CTR ((u32 *)(V7M_PROC_FTR_BASE + 0x04))
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#define V7M_PROC_REG_CCSIDR ((u32 *)(V7M_PROC_FTR_BASE + 0x08))
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#define MASK_NUM_WAYS GENMASK(12, 3)
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#define MASK_NUM_SETS GENMASK(27, 13)
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#define CLINE_SIZE_MASK GENMASK(2, 0)
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#define NUM_WAYS_SHIFT 3
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#define NUM_SETS_SHIFT 13
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#define V7M_PROC_REG_CSSELR ((u32 *)(V7M_PROC_FTR_BASE + 0x0C))
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#define SEL_I_OR_D BIT(0)
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enum cache_type {
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DCACHE,
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ICACHE,
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};
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/* PoU : Point of Unification, Poc: Point of Coherency */
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enum cache_action {
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INVALIDATE_POU, /* i-cache invalidate by address */
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INVALIDATE_POC, /* d-cache invalidate by address */
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INVALIDATE_SET_WAY, /* d-cache invalidate by sets/ways */
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FLUSH_POU, /* d-cache clean by address to the PoU */
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FLUSH_POC, /* d-cache clean by address to the PoC */
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FLUSH_SET_WAY, /* d-cache clean by sets/ways */
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FLUSH_INVAL_POC, /* d-cache clean & invalidate by addr to PoC */
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FLUSH_INVAL_SET_WAY, /* d-cache clean & invalidate by set/ways */
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};
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#ifndef CONFIG_SYS_DCACHE_OFF
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struct dcache_config {
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u32 ways;
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u32 sets;
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};
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static void get_cache_ways_sets(struct dcache_config *cache)
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{
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u32 cache_size_id = readl(V7M_PROC_REG_CCSIDR);
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cache->ways = (cache_size_id & MASK_NUM_WAYS) >> NUM_WAYS_SHIFT;
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cache->sets = (cache_size_id & MASK_NUM_SETS) >> NUM_SETS_SHIFT;
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}
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/*
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* Return the io register to perform required cache action like clean or clean
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* & invalidate by sets/ways.
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*/
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static u32 *get_action_reg_set_ways(enum cache_action action)
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{
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switch (action) {
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case INVALIDATE_SET_WAY:
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return V7M_CACHE_REG_DCISW;
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case FLUSH_SET_WAY:
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return V7M_CACHE_REG_DCCSW;
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case FLUSH_INVAL_SET_WAY:
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return V7M_CACHE_REG_DCCISW;
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default:
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break;
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};
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return NULL;
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}
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/*
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* Return the io register to perform required cache action like clean or clean
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* & invalidate by adddress or range.
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*/
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static u32 *get_action_reg_range(enum cache_action action)
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{
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switch (action) {
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case INVALIDATE_POU:
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return V7M_CACHE_REG_ICIMVALU;
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case INVALIDATE_POC:
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return V7M_CACHE_REG_DCIMVAC;
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case FLUSH_POU:
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return V7M_CACHE_REG_DCCMVAU;
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case FLUSH_POC:
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return V7M_CACHE_REG_DCCMVAC;
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case FLUSH_INVAL_POC:
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return V7M_CACHE_REG_DCCIMVAC;
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default:
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break;
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}
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return NULL;
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}
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static u32 get_cline_size(enum cache_type type)
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{
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u32 size;
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if (type == DCACHE)
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clrbits_le32(V7M_PROC_REG_CSSELR, BIT(SEL_I_OR_D));
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else if (type == ICACHE)
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setbits_le32(V7M_PROC_REG_CSSELR, BIT(SEL_I_OR_D));
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/* Make sure cache selection is effective for next memory access */
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dsb();
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size = readl(V7M_PROC_REG_CCSIDR) & CLINE_SIZE_MASK;
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/* Size enocoded as 2 less than log(no_of_words_in_cache_line) base 2 */
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size = 1 << (size + 2);
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debug("cache line size is %d\n", size);
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return size;
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}
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/* Perform the action like invalidate/clean on a range of cache addresses */
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static int action_cache_range(enum cache_action action, u32 start_addr,
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int64_t size)
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{
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u32 cline_size;
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u32 *action_reg;
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enum cache_type type;
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action_reg = get_action_reg_range(action);
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if (!action_reg)
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return -EINVAL;
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if (action == INVALIDATE_POU)
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type = ICACHE;
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else
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type = DCACHE;
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/* Cache line size is minium size for the cache action */
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cline_size = get_cline_size(type);
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/* Align start address to cache line boundary */
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start_addr &= ~(cline_size - 1);
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debug("total size for cache action = %llx\n", size);
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do {
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writel(start_addr, action_reg);
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size -= cline_size;
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start_addr += cline_size;
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} while (size > cline_size);
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/* Make sure cache action is effective for next memory access */
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dsb();
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isb(); /* Make sure instruction stream sees it */
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debug("cache action on range done\n");
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return 0;
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}
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/* Perform the action like invalidate/clean on all cached addresses */
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static int action_dcache_all(enum cache_action action)
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{
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struct dcache_config cache;
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u32 *action_reg;
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int i, j;
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action_reg = get_action_reg_set_ways(action);
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if (!action_reg)
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return -EINVAL;
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clrbits_le32(V7M_PROC_REG_CSSELR, BIT(SEL_I_OR_D));
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/* Make sure cache selection is effective for next memory access */
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dsb();
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get_cache_ways_sets(&cache); /* Get number of ways & sets */
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debug("cache: ways= %d, sets= %d\n", cache.ways + 1, cache.sets + 1);
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for (i = cache.sets; i >= 0; i--) {
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for (j = cache.ways; j >= 0; j--) {
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writel((j << WAYS_SHIFT) | (i << SETS_SHIFT),
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action_reg);
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}
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}
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/* Make sure cache action is effective for next memory access */
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dsb();
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isb(); /* Make sure instruction stream sees it */
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return 0;
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}
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void dcache_enable(void)
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{
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if (dcache_status()) /* return if cache already enabled */
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return;
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if (action_dcache_all(INVALIDATE_SET_WAY)) {
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printf("ERR: D-cache not enabled\n");
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return;
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}
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setbits_le32(&V7M_SCB->ccr, BIT(V7M_CCR_DCACHE));
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/* Make sure cache action is effective for next memory access */
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dsb();
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isb(); /* Make sure instruction stream sees it */
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}
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void dcache_disable(void)
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{
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if (!dcache_status())
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return;
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/* if dcache is enabled-> dcache disable & then flush */
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if (action_dcache_all(FLUSH_SET_WAY)) {
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printf("ERR: D-cache not flushed\n");
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return;
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}
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clrbits_le32(&V7M_SCB->ccr, BIT(V7M_CCR_DCACHE));
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/* Make sure cache action is effective for next memory access */
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dsb();
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isb(); /* Make sure instruction stream sees it */
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}
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int dcache_status(void)
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{
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return (readl(&V7M_SCB->ccr) & BIT(V7M_CCR_DCACHE)) != 0;
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}
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void invalidate_dcache_range(unsigned long start, unsigned long stop)
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{
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if (action_cache_range(INVALIDATE_POC, start, stop - start)) {
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printf("ERR: D-cache not invalidated\n");
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return;
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}
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}
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void flush_dcache_range(unsigned long start, unsigned long stop)
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{
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if (action_cache_range(FLUSH_POC, start, stop - start)) {
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printf("ERR: D-cache not flushed\n");
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return;
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}
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}
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void flush_dcache_all(void)
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{
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if (action_dcache_all(FLUSH_SET_WAY)) {
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printf("ERR: D-cache not flushed\n");
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return;
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}
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}
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void invalidate_dcache_all(void)
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{
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if (action_dcache_all(INVALIDATE_SET_WAY)) {
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printf("ERR: D-cache not invalidated\n");
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return;
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}
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}
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#else
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void dcache_enable(void)
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{
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return;
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}
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void dcache_disable(void)
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{
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return;
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}
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int dcache_status(void)
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{
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return 0;
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}
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void flush_dcache_all(void)
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{
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}
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void invalidate_dcache_all(void)
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{
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}
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#endif
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#ifndef CONFIG_SYS_ICACHE_OFF
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void invalidate_icache_all(void)
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{
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writel(INVAL_ICACHE_POU, V7M_CACHE_REG_ICIALLU);
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/* Make sure cache action is effective for next memory access */
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dsb();
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isb(); /* Make sure instruction stream sees it */
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}
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void icache_enable(void)
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{
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if (icache_status())
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return;
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invalidate_icache_all();
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setbits_le32(&V7M_SCB->ccr, BIT(V7M_CCR_ICACHE));
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/* Make sure cache action is effective for next memory access */
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dsb();
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isb(); /* Make sure instruction stream sees it */
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}
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int icache_status(void)
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{
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return (readl(&V7M_SCB->ccr) & BIT(V7M_CCR_ICACHE)) != 0;
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}
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void icache_disable(void)
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{
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if (!icache_status())
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return;
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isb(); /* flush pipeline */
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clrbits_le32(&V7M_SCB->ccr, BIT(V7M_CCR_ICACHE));
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isb(); /* subsequent instructions fetch see cache disable effect */
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}
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#else
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void icache_enable(void)
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{
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return;
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}
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void icache_disable(void)
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{
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return;
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}
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int icache_status(void)
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{
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return 0;
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}
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#endif
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void enable_caches(void)
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{
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#ifndef CONFIG_SYS_ICACHE_OFF
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icache_enable();
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#endif
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#ifndef CONFIG_SYS_DCACHE_OFF
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dcache_enable();
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#endif
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}
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