mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
113 lines
2.7 KiB
ArmAsm
113 lines
2.7 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* armboot - Startup Code for ARM926EJS CPU-core
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*
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* Copyright (c) 2003 Texas Instruments
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*
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* ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
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*
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* Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
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* Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
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* Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
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* Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
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* Copyright (c) 2003 Kshitij <kshitij@ti.com>
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* Copyright (c) 2010 Albert Aribaud <albert.u.boot@aribaud.net>
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*/
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#include <asm-offsets.h>
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#include <config.h>
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#include <common.h>
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/*
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*************************************************************************
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*
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* Startup Code (reset vector)
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*
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* do important init only if we don't start from memory!
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* setup Memory and board specific bits prior to relocation.
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* relocate armboot to ram
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* setup stack
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*
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*************************************************************************
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*/
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.globl reset
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reset:
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/*
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* set the cpu to SVC32 mode
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*/
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mrs r0,cpsr
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bic r0,r0,#0x1f
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orr r0,r0,#0xd3
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msr cpsr,r0
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/*
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* we do sys-critical inits only at reboot,
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* not when booting from ram!
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*/
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT
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bl cpu_init_crit
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#endif
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bl _main
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/*------------------------------------------------------------------------------*/
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.globl c_runtime_cpu_setup
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c_runtime_cpu_setup:
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bx lr
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/*
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*************************************************************************
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*
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* CPU_init_critical registers
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*
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* setup important registers
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* setup memory timing
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*
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*************************************************************************
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*/
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT
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cpu_init_crit:
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/*
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* flush D cache before disabling it
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*/
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mov r0, #0
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flush_dcache:
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mrc p15, 0, r15, c7, c10, 3
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bne flush_dcache
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mcr p15, 0, r0, c8, c7, 0 /* invalidate TLB */
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mcr p15, 0, r0, c7, c5, 0 /* invalidate I Cache */
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/*
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* disable MMU and D cache
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* enable I cache if CONFIG_SYS_ICACHE_OFF is not defined
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*/
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mrc p15, 0, r0, c1, c0, 0
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bic r0, r0, #0x00000300 /* clear bits 9:8 (---- --RS) */
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bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */
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#ifdef CONFIG_SYS_EXCEPTION_VECTORS_HIGH
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orr r0, r0, #0x00002000 /* set bit 13 (--V- ----) */
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#else
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bic r0, r0, #0x00002000 /* clear bit 13 (--V- ----) */
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#endif
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orr r0, r0, #0x00000002 /* set bit 1 (A) Align */
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#ifndef CONFIG_SYS_ICACHE_OFF
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orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
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#endif
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mcr p15, 0, r0, c1, c0, 0
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT_ONLY
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/*
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* Go setup Memory and board specific bits prior to relocation.
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*/
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mov r4, lr /* perserve link reg across call */
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bl lowlevel_init /* go setup pll,mux,memory */
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mov lr, r4 /* restore link */
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#endif
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mov pc, lr /* back to my caller */
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#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
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