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![Stephen Warren](/assets/img/avatar_default.png)
In tegra20_slink.c, the set_mode() function may be executed before the
SPI bus is claimed the first time, and hence the clocks to the SPI
controller may not be running. If so, any register read/write at this
time will hang the CPU. Fix this by ensuring the clock is running as soon
as the driver is probed. This is observed on the Tegra30 Beaver board.
Apply the same clock initialization fix to all other Tegra SPI drivers so
that if set_mode() is ever implemented there, the same bug will not appear.
Note that tegra114_spi.c already operates in this fashion.
The clock manipulation code is copied from claim_bus() to probe() rather
than moved. This ensures that any calls to set_speed() take effect; the
clock can't be set once during probe and left unchanged.
Fixes: 5cb1b7b395
("spi: tegra20: Add support for mode selection")
Cc: Mirza Krak <mirza.krak@hostmobility.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
358 lines
9.5 KiB
C
358 lines
9.5 KiB
C
/*
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* Copyright (c) 2010-2013 NVIDIA Corporation
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* With help from the mpc8xxx SPI driver
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* With more help from omap3_spi SPI driver
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <asm/io.h>
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#include <asm/gpio.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/pinmux.h>
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#include <asm/arch-tegra/clk_rst.h>
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#include <spi.h>
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#include <fdtdec.h>
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#include "tegra_spi.h"
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DECLARE_GLOBAL_DATA_PTR;
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#define SPI_CMD_GO BIT(30)
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#define SPI_CMD_ACTIVE_SCLK_SHIFT 26
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#define SPI_CMD_ACTIVE_SCLK_MASK (3 << SPI_CMD_ACTIVE_SCLK_SHIFT)
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#define SPI_CMD_CK_SDA BIT(21)
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#define SPI_CMD_ACTIVE_SDA_SHIFT 18
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#define SPI_CMD_ACTIVE_SDA_MASK (3 << SPI_CMD_ACTIVE_SDA_SHIFT)
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#define SPI_CMD_CS_POL BIT(16)
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#define SPI_CMD_TXEN BIT(15)
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#define SPI_CMD_RXEN BIT(14)
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#define SPI_CMD_CS_VAL BIT(13)
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#define SPI_CMD_CS_SOFT BIT(12)
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#define SPI_CMD_CS_DELAY BIT(9)
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#define SPI_CMD_CS3_EN BIT(8)
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#define SPI_CMD_CS2_EN BIT(7)
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#define SPI_CMD_CS1_EN BIT(6)
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#define SPI_CMD_CS0_EN BIT(5)
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#define SPI_CMD_BIT_LENGTH BIT(4)
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#define SPI_CMD_BIT_LENGTH_MASK GENMASK(4, 0)
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#define SPI_STAT_BSY BIT(31)
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#define SPI_STAT_RDY BIT(30)
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#define SPI_STAT_RXF_FLUSH BIT(29)
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#define SPI_STAT_TXF_FLUSH BIT(28)
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#define SPI_STAT_RXF_UNR BIT(27)
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#define SPI_STAT_TXF_OVF BIT(26)
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#define SPI_STAT_RXF_EMPTY BIT(25)
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#define SPI_STAT_RXF_FULL BIT(24)
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#define SPI_STAT_TXF_EMPTY BIT(23)
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#define SPI_STAT_TXF_FULL BIT(22)
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#define SPI_STAT_SEL_TXRX_N BIT(16)
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#define SPI_STAT_CUR_BLKCNT BIT(15)
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#define SPI_TIMEOUT 1000
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#define TEGRA_SPI_MAX_FREQ 52000000
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struct spi_regs {
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u32 command; /* SPI_COMMAND_0 register */
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u32 status; /* SPI_STATUS_0 register */
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u32 rx_cmp; /* SPI_RX_CMP_0 register */
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u32 dma_ctl; /* SPI_DMA_CTL_0 register */
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u32 tx_fifo; /* SPI_TX_FIFO_0 register */
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u32 rsvd[3]; /* offsets 0x14 to 0x1F reserved */
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u32 rx_fifo; /* SPI_RX_FIFO_0 register */
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};
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struct tegra20_sflash_priv {
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struct spi_regs *regs;
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unsigned int freq;
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unsigned int mode;
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int periph_id;
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int valid;
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int last_transaction_us;
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};
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int tegra20_sflash_cs_info(struct udevice *bus, unsigned int cs,
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struct spi_cs_info *info)
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{
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/* Tegra20 SPI-Flash - only 1 device ('bus/cs') */
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if (cs != 0)
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return -ENODEV;
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else
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return 0;
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}
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static int tegra20_sflash_ofdata_to_platdata(struct udevice *bus)
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{
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struct tegra_spi_platdata *plat = bus->platdata;
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const void *blob = gd->fdt_blob;
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int node = bus->of_offset;
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plat->base = dev_get_addr(bus);
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plat->periph_id = clock_decode_periph_id(blob, node);
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if (plat->periph_id == PERIPH_ID_NONE) {
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debug("%s: could not decode periph id %d\n", __func__,
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plat->periph_id);
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return -FDT_ERR_NOTFOUND;
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}
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/* Use 500KHz as a suitable default */
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plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
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500000);
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plat->deactivate_delay_us = fdtdec_get_int(blob, node,
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"spi-deactivate-delay", 0);
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debug("%s: base=%#08lx, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n",
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__func__, plat->base, plat->periph_id, plat->frequency,
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plat->deactivate_delay_us);
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return 0;
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}
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static int tegra20_sflash_probe(struct udevice *bus)
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{
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struct tegra_spi_platdata *plat = dev_get_platdata(bus);
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struct tegra20_sflash_priv *priv = dev_get_priv(bus);
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priv->regs = (struct spi_regs *)plat->base;
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priv->last_transaction_us = timer_get_us();
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priv->freq = plat->frequency;
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priv->periph_id = plat->periph_id;
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/* Change SPI clock to correct frequency, PLLP_OUT0 source */
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clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH,
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priv->freq);
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return 0;
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}
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static int tegra20_sflash_claim_bus(struct udevice *dev)
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{
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struct udevice *bus = dev->parent;
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struct tegra20_sflash_priv *priv = dev_get_priv(bus);
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struct spi_regs *regs = priv->regs;
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u32 reg;
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/* Change SPI clock to correct frequency, PLLP_OUT0 source */
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clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH,
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priv->freq);
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/* Clear stale status here */
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reg = SPI_STAT_RDY | SPI_STAT_RXF_FLUSH | SPI_STAT_TXF_FLUSH | \
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SPI_STAT_RXF_UNR | SPI_STAT_TXF_OVF;
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writel(reg, ®s->status);
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debug("%s: STATUS = %08x\n", __func__, readl(®s->status));
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/*
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* Use sw-controlled CS, so we can clock in data after ReadID, etc.
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*/
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reg = (priv->mode & 1) << SPI_CMD_ACTIVE_SDA_SHIFT;
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if (priv->mode & 2)
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reg |= 1 << SPI_CMD_ACTIVE_SCLK_SHIFT;
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clrsetbits_le32(®s->command, SPI_CMD_ACTIVE_SCLK_MASK |
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SPI_CMD_ACTIVE_SDA_MASK, SPI_CMD_CS_SOFT | reg);
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debug("%s: COMMAND = %08x\n", __func__, readl(®s->command));
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/*
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* SPI pins on Tegra20 are muxed - change pinmux later due to UART
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* issue.
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*/
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pinmux_set_func(PMUX_PINGRP_GMD, PMUX_FUNC_SFLASH);
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pinmux_tristate_disable(PMUX_PINGRP_LSPI);
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pinmux_set_func(PMUX_PINGRP_GMC, PMUX_FUNC_SFLASH);
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return 0;
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}
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static void spi_cs_activate(struct udevice *dev)
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{
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struct udevice *bus = dev->parent;
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struct tegra_spi_platdata *pdata = dev_get_platdata(bus);
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struct tegra20_sflash_priv *priv = dev_get_priv(bus);
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/* If it's too soon to do another transaction, wait */
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if (pdata->deactivate_delay_us &&
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priv->last_transaction_us) {
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ulong delay_us; /* The delay completed so far */
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delay_us = timer_get_us() - priv->last_transaction_us;
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if (delay_us < pdata->deactivate_delay_us)
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udelay(pdata->deactivate_delay_us - delay_us);
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}
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/* CS is negated on Tegra, so drive a 1 to get a 0 */
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setbits_le32(&priv->regs->command, SPI_CMD_CS_VAL);
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}
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static void spi_cs_deactivate(struct udevice *dev)
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{
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struct udevice *bus = dev->parent;
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struct tegra_spi_platdata *pdata = dev_get_platdata(bus);
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struct tegra20_sflash_priv *priv = dev_get_priv(bus);
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/* CS is negated on Tegra, so drive a 0 to get a 1 */
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clrbits_le32(&priv->regs->command, SPI_CMD_CS_VAL);
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/* Remember time of this transaction so we can honour the bus delay */
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if (pdata->deactivate_delay_us)
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priv->last_transaction_us = timer_get_us();
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}
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static int tegra20_sflash_xfer(struct udevice *dev, unsigned int bitlen,
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const void *data_out, void *data_in,
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unsigned long flags)
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{
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struct udevice *bus = dev->parent;
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struct tegra20_sflash_priv *priv = dev_get_priv(bus);
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struct spi_regs *regs = priv->regs;
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u32 reg, tmpdout, tmpdin = 0;
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const u8 *dout = data_out;
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u8 *din = data_in;
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int num_bytes;
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int ret;
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debug("%s: slave %u:%u dout %p din %p bitlen %u\n",
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__func__, bus->seq, spi_chip_select(dev), dout, din, bitlen);
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if (bitlen % 8)
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return -1;
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num_bytes = bitlen / 8;
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ret = 0;
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reg = readl(®s->status);
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writel(reg, ®s->status); /* Clear all SPI events via R/W */
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debug("spi_xfer entry: STATUS = %08x\n", reg);
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reg = readl(®s->command);
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reg |= SPI_CMD_TXEN | SPI_CMD_RXEN;
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writel(reg, ®s->command);
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debug("spi_xfer: COMMAND = %08x\n", readl(®s->command));
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if (flags & SPI_XFER_BEGIN)
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spi_cs_activate(dev);
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/* handle data in 32-bit chunks */
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while (num_bytes > 0) {
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int bytes;
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int is_read = 0;
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int tm, i;
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tmpdout = 0;
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bytes = (num_bytes > 4) ? 4 : num_bytes;
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if (dout != NULL) {
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for (i = 0; i < bytes; ++i)
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tmpdout = (tmpdout << 8) | dout[i];
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}
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num_bytes -= bytes;
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if (dout)
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dout += bytes;
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clrsetbits_le32(®s->command, SPI_CMD_BIT_LENGTH_MASK,
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bytes * 8 - 1);
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writel(tmpdout, ®s->tx_fifo);
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setbits_le32(®s->command, SPI_CMD_GO);
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/*
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* Wait for SPI transmit FIFO to empty, or to time out.
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* The RX FIFO status will be read and cleared last
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*/
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for (tm = 0, is_read = 0; tm < SPI_TIMEOUT; ++tm) {
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u32 status;
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status = readl(®s->status);
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/* We can exit when we've had both RX and TX activity */
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if (is_read && (status & SPI_STAT_TXF_EMPTY))
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break;
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if ((status & (SPI_STAT_BSY | SPI_STAT_RDY)) !=
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SPI_STAT_RDY)
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tm++;
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else if (!(status & SPI_STAT_RXF_EMPTY)) {
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tmpdin = readl(®s->rx_fifo);
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is_read = 1;
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/* swap bytes read in */
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if (din != NULL) {
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for (i = bytes - 1; i >= 0; --i) {
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din[i] = tmpdin & 0xff;
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tmpdin >>= 8;
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}
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din += bytes;
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}
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}
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}
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if (tm >= SPI_TIMEOUT)
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ret = tm;
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/* clear ACK RDY, etc. bits */
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writel(readl(®s->status), ®s->status);
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}
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if (flags & SPI_XFER_END)
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spi_cs_deactivate(dev);
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debug("spi_xfer: transfer ended. Value=%08x, status = %08x\n",
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tmpdin, readl(®s->status));
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if (ret) {
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printf("spi_xfer: timeout during SPI transfer, tm %d\n", ret);
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return -1;
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}
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return 0;
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}
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static int tegra20_sflash_set_speed(struct udevice *bus, uint speed)
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{
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struct tegra_spi_platdata *plat = bus->platdata;
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struct tegra20_sflash_priv *priv = dev_get_priv(bus);
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if (speed > plat->frequency)
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speed = plat->frequency;
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priv->freq = speed;
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debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq);
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return 0;
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}
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static int tegra20_sflash_set_mode(struct udevice *bus, uint mode)
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{
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struct tegra20_sflash_priv *priv = dev_get_priv(bus);
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priv->mode = mode;
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debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode);
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return 0;
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}
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static const struct dm_spi_ops tegra20_sflash_ops = {
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.claim_bus = tegra20_sflash_claim_bus,
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.xfer = tegra20_sflash_xfer,
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.set_speed = tegra20_sflash_set_speed,
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.set_mode = tegra20_sflash_set_mode,
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.cs_info = tegra20_sflash_cs_info,
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};
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static const struct udevice_id tegra20_sflash_ids[] = {
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{ .compatible = "nvidia,tegra20-sflash" },
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{ }
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};
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U_BOOT_DRIVER(tegra20_sflash) = {
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.name = "tegra20_sflash",
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.id = UCLASS_SPI,
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.of_match = tegra20_sflash_ids,
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.ops = &tegra20_sflash_ops,
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.ofdata_to_platdata = tegra20_sflash_ofdata_to_platdata,
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.platdata_auto_alloc_size = sizeof(struct tegra_spi_platdata),
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.priv_auto_alloc_size = sizeof(struct tegra20_sflash_priv),
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.probe = tegra20_sflash_probe,
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};
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