u-boot-brain/board/xilinx
Siva Durga Prasad Paladugu 83bf2ff03d arm64: zynqmp: Correct EG/EV part detection logic
The vcu disable bit in efuse ipdisable register is valid only
if PL powered up so, consider PL powerup status for determing
EG/EV part. If PL is not powered up, ignore EG/EV part of string.
The PL powerup status will be filled by pmufw based on PL PROGB
status in the 9th bit of version field.

Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2018-03-23 09:34:44 +01:00
..
microblaze-generic board_f: Drop setup_dram_config() wrapper 2017-04-05 16:36:51 -04:00
zynq arm: zynq: Wire watchdog internals 2018-03-23 09:34:43 +01:00
zynqmp arm64: zynqmp: Correct EG/EV part detection logic 2018-03-23 09:34:44 +01:00