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![Wolfgang Denk](/assets/img/avatar_default.png)
Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
185 lines
5.0 KiB
C
185 lines
5.0 KiB
C
/*
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* Copyright (C) 2003 Travis B. Sawyer <travis.sawyer@sandburst.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/processor.h>
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#include <spd_sdram.h>
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#include <i2c.h>
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#include <net.h>
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DECLARE_GLOBAL_DATA_PTR;
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int board_early_init_f(void)
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{
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unsigned long sdrreg;
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/*
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* Enable GPIO for pins 18 - 24
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* 18 = SEEPROM_WP
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* 19 = #M_RST
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* 20 = #MONARCH
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* 21 = #LED_ALARM
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* 22 = #LED_ACT
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* 23 = #LED_STATUS1
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* 24 = #LED_STATUS2
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*/
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mfsdr(SDR0_PFC0, sdrreg);
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mtsdr(SDR0_PFC0, (sdrreg & ~SDR0_PFC0_TRE_ENABLE) | 0x00003e00);
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out32(CONFIG_SYS_GPIO_BASE + 0x018, (USR_LED0 | USR_LED1 | USR_LED2 | USR_LED3));
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LED0_OFF();
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LED1_OFF();
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LED2_OFF();
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LED3_OFF();
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/* Setup the external bus controller/chip selects */
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mtebc(PB0AP, 0x04055200); /* 16MB Strata FLASH */
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mtebc(PB0CR, 0xff098000); /* BAS=0xff0 16MB R/W 8-bit */
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mtebc(PB1AP, 0x04055200); /* 512KB Socketed AMD FLASH */
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mtebc(PB1CR, 0xfe018000); /* BAS=0xfe0 1MB R/W 8-bit */
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mtebc(PB6AP, 0x05006400); /* 32-64MB AMD MirrorBit FLASH */
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mtebc(PB6CR, 0xf00da000); /* BAS=0xf00 64MB R/W i6-bit */
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mtebc(PB7AP, 0x05006400); /* 32-64MB AMD MirrorBit FLASH */
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mtebc(PB7CR, 0xf40da000); /* BAS=0xf40 64MB R/W 16-bit */
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/*
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* Setup the interrupt controller polarities, triggers, etc.
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*
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* Because of the interrupt handling rework to handle 440GX interrupts
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* with the common code, we needed to change names of the UIC registers.
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* Here the new relationship:
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*
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* U-Boot name 440GX name
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* -----------------------
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* UIC0 UICB0
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* UIC1 UIC0
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* UIC2 UIC1
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* UIC3 UIC2
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*/
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mtdcr(UIC1SR, 0xffffffff); /* clear all */
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mtdcr(UIC1ER, 0x00000000); /* disable all */
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mtdcr(UIC1CR, 0x00000003); /* SMI & UIC1 crit are critical */
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mtdcr(UIC1PR, 0xfffffe00); /* per ref-board manual */
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mtdcr(UIC1TR, 0x01c00000); /* per ref-board manual */
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mtdcr(UIC1VR, 0x00000001); /* int31 highest, base=0x000 */
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mtdcr(UIC1SR, 0xffffffff); /* clear all */
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mtdcr(UIC2SR, 0xffffffff); /* clear all */
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mtdcr(UIC2ER, 0x00000000); /* disable all */
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mtdcr(UIC2CR, 0x00000000); /* all non-critical */
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mtdcr(UIC2PR, 0xffffc0ff); /* per ref-board manual */
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mtdcr(UIC2TR, 0x00ff8000); /* per ref-board manual */
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mtdcr(UIC2VR, 0x00000001); /* int31 highest, base=0x000 */
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mtdcr(UIC2SR, 0xffffffff); /* clear all */
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mtdcr(UIC3SR, 0xffffffff); /* clear all */
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mtdcr(UIC3ER, 0x00000000); /* disable all */
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mtdcr(UIC3CR, 0x00000000); /* all non-critical */
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mtdcr(UIC3PR, 0xffffffff); /* per ref-board manual */
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mtdcr(UIC3TR, 0x00ff8c0f); /* per ref-board manual */
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mtdcr(UIC3VR, 0x00000001); /* int31 highest, base=0x000 */
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mtdcr(UIC3SR, 0xffffffff); /* clear all */
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mtdcr(UIC0SR, 0xfc000000); /* clear all */
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mtdcr(UIC0ER, 0x00000000); /* disable all */
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mtdcr(UIC0CR, 0x00000000); /* all non-critical */
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mtdcr(UIC0PR, 0xfc000000); /* */
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mtdcr(UIC0TR, 0x00000000); /* */
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mtdcr(UIC0VR, 0x00000001); /* */
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LED0_ON();
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return 0;
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}
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int checkboard(void)
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{
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char buf[64];
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int i;
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printf("Board: X-ES %s PMC SBC\n", CONFIG_SYS_BOARD_NAME);
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printf(" ");
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i = getenv_f("board_rev", buf, sizeof(buf));
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if (i > 0)
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printf("Rev %s, ", buf);
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i = getenv_f("serial#", buf, sizeof(buf));
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if (i > 0)
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printf("Serial# %s, ", buf);
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i = getenv_f("board_cfg", buf, sizeof(buf));
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if (i > 0)
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printf("Cfg %s", buf);
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printf("\n");
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return 0;
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}
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phys_size_t initdram(int board_type)
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{
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return spd_sdram();
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}
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/*
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* Override weak pci_pre_init()
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*
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* This routine is called just prior to registering the hose and gives
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* the board the opportunity to check things. Returning a value of zero
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* indicates that things are bad & PCI initialization should be aborted.
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*
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* Different boards may wish to customize the pci controller structure
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* (add regions, override default access routines, etc) or perform
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* certain pre-initialization actions.
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*/
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#if defined(CONFIG_PCI)
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int pci_pre_init(struct pci_controller * hose)
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{
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unsigned long strap;
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/* See if we're supposed to setup the pci */
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mfsdr(SDR0_SDSTP1, strap);
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if ((strap & 0x00010000) == 0)
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return 0;
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#if defined(CONFIG_SYS_PCI_FORCE_PCI_CONV)
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/* Setup System Device Register PCIL0_XCR */
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mfsdr(SDR0_XCR, strap);
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strap &= 0x0f000000;
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mtsdr(SDR0_XCR, strap);
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#endif
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return 1;
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}
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#endif /* defined(CONFIG_PCI) */
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#if defined(CONFIG_PCI)
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/*
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* Override weak is_pci_host()
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*
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* This routine is called to determine if a pci scan should be
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* performed. With various hardware environments (especially cPCI and
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* PPMC) it's insufficient to depend on the state of the arbiter enable
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* bit in the strap register, or generic host/adapter assumptions.
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*
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* Rather than hard-code a bad assumption in the general 440 code, the
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* 440 pci code requires the board to decide at runtime.
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*
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* Return 0 for adapter mode, non-zero for host (monarch) mode.
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*/
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int is_pci_host(struct pci_controller *hose)
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{
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return ((in32(CONFIG_SYS_GPIO_BASE + 0x1C) & 0x00000800) == 0);
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}
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#endif /* defined(CONFIG_PCI) */
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#ifdef CONFIG_POST
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/*
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* Returns 1 if keys pressed to start the power-on long-running tests
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* Called from board_init_f().
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*/
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int post_hotkeys_pressed(void)
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{
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return ctrlc();
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}
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#endif
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