mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-14 15:16:16 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
152 lines
4.6 KiB
C
152 lines
4.6 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
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* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
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*/
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/*
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* PCI Configuration space access support
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*/
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#include <common.h>
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#include <pci.h>
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#include <asm/io.h>
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#include <asm/immap.h>
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#if defined(CONFIG_PCI)
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/* System RAM mapped over PCI */
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#define CONFIG_SYS_PCI_SYS_MEM_BUS CONFIG_SYS_SDRAM_BASE
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#define CONFIG_SYS_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE
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#define CONFIG_SYS_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024)
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#define cfg_read(val, addr, type, op) *val = op((type)(addr));
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#define cfg_write(val, addr, type, op) op((type *)(addr), (val));
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#define PCI_OP(rw, size, type, op, mask) \
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int pci_##rw##_cfg_##size(struct pci_controller *hose, \
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pci_dev_t dev, int offset, type val) \
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{ \
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u32 addr = 0; \
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u16 cfg_type = 0; \
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addr = ((offset & 0xfc) | cfg_type | (dev) | 0x80000000); \
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out_be32(hose->cfg_addr, addr); \
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cfg_##rw(val, hose->cfg_data + (offset & mask), type, op); \
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out_be32(hose->cfg_addr, addr & 0x7fffffff); \
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return 0; \
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}
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PCI_OP(read, byte, u8 *, in_8, 3)
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PCI_OP(read, word, u16 *, in_le16, 2)
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PCI_OP(read, dword, u32 *, in_le32, 0)
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PCI_OP(write, byte, u8, out_8, 3)
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PCI_OP(write, word, u16, out_le16, 2)
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PCI_OP(write, dword, u32, out_le32, 0)
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void pci_mcf5445x_init(struct pci_controller *hose)
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{
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pci_t *pci = (pci_t *)MMAP_PCI;
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pciarb_t *pciarb = (pciarb_t *)MMAP_PCIARB;
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gpio_t *gpio = (gpio_t *) MMAP_GPIO;
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u32 barEn = 0;
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out_be32(&pciarb->acr, 0x001f001f);
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/* Set PCIGNT1, PCIREQ1, PCIREQ0/PCIGNTIN, PCIGNT0/PCIREQOUT,
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PCIREQ2, PCIGNT2 */
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out_be16(&gpio->par_pci,
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GPIO_PAR_PCI_GNT3_GNT3 | GPIO_PAR_PCI_GNT2 |
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GPIO_PAR_PCI_GNT1 | GPIO_PAR_PCI_GNT0 |
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GPIO_PAR_PCI_REQ3_REQ3 | GPIO_PAR_PCI_REQ2 |
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GPIO_PAR_PCI_REQ1 | GPIO_PAR_PCI_REQ0);
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/* Assert reset bit */
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setbits_be32(&pci->gscr, PCI_GSCR_PR);
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setbits_be32(&pci->tcr1, PCI_TCR1_P);
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/* Initiator windows */
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out_be32(&pci->iw0btar,
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CONFIG_SYS_PCI_MEM_PHYS | (CONFIG_SYS_PCI_MEM_PHYS >> 16));
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out_be32(&pci->iw1btar,
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CONFIG_SYS_PCI_IO_PHYS | (CONFIG_SYS_PCI_IO_PHYS >> 16));
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out_be32(&pci->iw2btar,
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CONFIG_SYS_PCI_CFG_PHYS | (CONFIG_SYS_PCI_CFG_PHYS >> 16));
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out_be32(&pci->iwcr,
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PCI_IWCR_W0C_EN | PCI_IWCR_W1C_EN | PCI_IWCR_W1C_IO |
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PCI_IWCR_W2C_EN | PCI_IWCR_W2C_IO);
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out_be32(&pci->icr, 0);
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/* Enable bus master and mem access */
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out_be32(&pci->scr, PCI_SCR_B | PCI_SCR_M);
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/* Cache line size and master latency */
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out_be32(&pci->cr1, PCI_CR1_CLS(8) | PCI_CR1_LTMR(0xF8));
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out_be32(&pci->cr2, 0);
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#ifdef CONFIG_SYS_PCI_BAR0
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out_be32(&pci->bar0, PCI_BAR_BAR0(CONFIG_SYS_PCI_BAR0));
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out_be32(&pci->tbatr0, CONFIG_SYS_PCI_TBATR0 | PCI_TBATR_EN);
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barEn |= PCI_TCR2_B0E;
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#endif
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#ifdef CONFIG_SYS_PCI_BAR1
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out_be32(&pci->bar1, PCI_BAR_BAR1(CONFIG_SYS_PCI_BAR1));
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out_be32(&pci->tbatr1, CONFIG_SYS_PCI_TBATR1 | PCI_TBATR_EN);
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barEn |= PCI_TCR2_B1E;
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#endif
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#ifdef CONFIG_SYS_PCI_BAR2
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out_be32(&pci->bar2, PCI_BAR_BAR2(CONFIG_SYS_PCI_BAR2));
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out_be32(&pci->tbatr2, CONFIG_SYS_PCI_TBATR2 | PCI_TBATR_EN);
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barEn |= PCI_TCR2_B2E;
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#endif
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#ifdef CONFIG_SYS_PCI_BAR3
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out_be32(&pci->bar3, PCI_BAR_BAR3(CONFIG_SYS_PCI_BAR3));
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out_be32(&pci->tbatr3, CONFIG_SYS_PCI_TBATR3 | PCI_TBATR_EN);
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barEn |= PCI_TCR2_B3E;
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#endif
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#ifdef CONFIG_SYS_PCI_BAR4
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out_be32(&pci->bar4, PCI_BAR_BAR4(CONFIG_SYS_PCI_BAR4));
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out_be32(&pci->tbatr4, CONFIG_SYS_PCI_TBATR4 | PCI_TBATR_EN);
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barEn |= PCI_TCR2_B4E;
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#endif
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#ifdef CONFIG_SYS_PCI_BAR5
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out_be32(&pci->bar5, PCI_BAR_BAR5(CONFIG_SYS_PCI_BAR5));
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out_be32(&pci->tbatr5, CONFIG_SYS_PCI_TBATR5 | PCI_TBATR_EN);
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barEn |= PCI_TCR2_B5E;
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#endif
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out_be32(&pci->tcr2, barEn);
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/* Deassert reset bit */
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clrbits_be32(&pci->gscr, PCI_GSCR_PR);
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udelay(1000);
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/* Enable PCI bus master support */
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hose->first_busno = 0;
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hose->last_busno = 0xff;
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pci_set_region(hose->regions + 0, CONFIG_SYS_PCI_MEM_BUS, CONFIG_SYS_PCI_MEM_PHYS,
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CONFIG_SYS_PCI_MEM_SIZE, PCI_REGION_MEM);
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pci_set_region(hose->regions + 1, CONFIG_SYS_PCI_IO_BUS, CONFIG_SYS_PCI_IO_PHYS,
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CONFIG_SYS_PCI_IO_SIZE, PCI_REGION_IO);
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pci_set_region(hose->regions + 2, CONFIG_SYS_PCI_SYS_MEM_BUS,
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CONFIG_SYS_PCI_SYS_MEM_PHYS, CONFIG_SYS_PCI_SYS_MEM_SIZE,
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PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
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hose->region_count = 3;
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hose->cfg_addr = &(pci->car);
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hose->cfg_data = (volatile unsigned char *)CONFIG_SYS_PCI_CFG_BUS;
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pci_set_ops(hose, pci_read_cfg_byte, pci_read_cfg_word,
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pci_read_cfg_dword, pci_write_cfg_byte, pci_write_cfg_word,
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pci_write_cfg_dword);
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/* Hose scan */
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pci_register_hose(hose);
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hose->last_busno = pci_hose_scan(hose);
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}
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#endif /* CONFIG_PCI */
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