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https://github.com/brain-hackers/u-boot-brain
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![Simon Glass](/assets/img/avatar_default.png)
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
614 lines
19 KiB
C
614 lines
19 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>
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*
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* VirtIO PCI bus transport driver
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* Ported from Linux drivers/virtio/virtio_pci*.c
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*/
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#include <common.h>
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#include <dm.h>
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#include <log.h>
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#include <virtio_types.h>
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#include <virtio.h>
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#include <virtio_ring.h>
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#include <dm/device.h>
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#include <linux/bug.h>
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#include <linux/compat.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include "virtio_pci.h"
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#define VIRTIO_PCI_DRV_NAME "virtio-pci.m"
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/* PCI device ID in the range 0x1040 to 0x107f */
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#define VIRTIO_PCI_VENDOR_ID 0x1af4
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#define VIRTIO_PCI_DEVICE_ID00 0x1040
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#define VIRTIO_PCI_DEVICE_ID01 0x1041
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#define VIRTIO_PCI_DEVICE_ID02 0x1042
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#define VIRTIO_PCI_DEVICE_ID03 0x1043
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#define VIRTIO_PCI_DEVICE_ID04 0x1044
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#define VIRTIO_PCI_DEVICE_ID05 0x1045
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#define VIRTIO_PCI_DEVICE_ID06 0x1046
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#define VIRTIO_PCI_DEVICE_ID07 0x1047
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#define VIRTIO_PCI_DEVICE_ID08 0x1048
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#define VIRTIO_PCI_DEVICE_ID09 0x1049
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#define VIRTIO_PCI_DEVICE_ID0A 0x104a
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#define VIRTIO_PCI_DEVICE_ID0B 0x104b
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#define VIRTIO_PCI_DEVICE_ID0C 0x104c
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#define VIRTIO_PCI_DEVICE_ID0D 0x104d
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#define VIRTIO_PCI_DEVICE_ID0E 0x104e
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#define VIRTIO_PCI_DEVICE_ID0F 0x104f
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#define VIRTIO_PCI_DEVICE_ID10 0x1050
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#define VIRTIO_PCI_DEVICE_ID11 0x1051
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#define VIRTIO_PCI_DEVICE_ID12 0x1052
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#define VIRTIO_PCI_DEVICE_ID13 0x1053
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#define VIRTIO_PCI_DEVICE_ID14 0x1054
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#define VIRTIO_PCI_DEVICE_ID15 0x1055
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#define VIRTIO_PCI_DEVICE_ID16 0x1056
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#define VIRTIO_PCI_DEVICE_ID17 0x1057
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#define VIRTIO_PCI_DEVICE_ID18 0x1058
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#define VIRTIO_PCI_DEVICE_ID19 0x1059
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#define VIRTIO_PCI_DEVICE_ID1A 0x105a
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#define VIRTIO_PCI_DEVICE_ID1B 0x105b
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#define VIRTIO_PCI_DEVICE_ID1C 0x105c
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#define VIRTIO_PCI_DEVICE_ID1D 0x105d
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#define VIRTIO_PCI_DEVICE_ID1E 0x105e
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#define VIRTIO_PCI_DEVICE_ID1F 0x105f
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#define VIRTIO_PCI_DEVICE_ID20 0x1060
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#define VIRTIO_PCI_DEVICE_ID21 0x1061
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#define VIRTIO_PCI_DEVICE_ID22 0x1062
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#define VIRTIO_PCI_DEVICE_ID23 0x1063
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#define VIRTIO_PCI_DEVICE_ID24 0x1064
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#define VIRTIO_PCI_DEVICE_ID25 0x1065
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#define VIRTIO_PCI_DEVICE_ID26 0x1066
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#define VIRTIO_PCI_DEVICE_ID27 0x1067
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#define VIRTIO_PCI_DEVICE_ID28 0x1068
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#define VIRTIO_PCI_DEVICE_ID29 0x1069
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#define VIRTIO_PCI_DEVICE_ID2A 0x106a
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#define VIRTIO_PCI_DEVICE_ID2B 0x106b
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#define VIRTIO_PCI_DEVICE_ID2C 0x106c
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#define VIRTIO_PCI_DEVICE_ID2D 0x106d
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#define VIRTIO_PCI_DEVICE_ID2E 0x106e
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#define VIRTIO_PCI_DEVICE_ID2F 0x106f
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#define VIRTIO_PCI_DEVICE_ID30 0x1070
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#define VIRTIO_PCI_DEVICE_ID31 0x1071
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#define VIRTIO_PCI_DEVICE_ID32 0x1072
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#define VIRTIO_PCI_DEVICE_ID33 0x1073
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#define VIRTIO_PCI_DEVICE_ID34 0x1074
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#define VIRTIO_PCI_DEVICE_ID35 0x1075
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#define VIRTIO_PCI_DEVICE_ID36 0x1076
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#define VIRTIO_PCI_DEVICE_ID37 0x1077
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#define VIRTIO_PCI_DEVICE_ID38 0x1078
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#define VIRTIO_PCI_DEVICE_ID39 0x1079
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#define VIRTIO_PCI_DEVICE_ID3A 0x107a
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#define VIRTIO_PCI_DEVICE_ID3B 0x107b
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#define VIRTIO_PCI_DEVICE_ID3C 0x107c
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#define VIRTIO_PCI_DEVICE_ID3D 0x107d
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#define VIRTIO_PCI_DEVICE_ID3E 0x107e
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#define VIRTIO_PCI_DEVICE_ID3F 0x107f
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/**
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* virtio pci transport driver private data
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*
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* @common: pci transport device common register block base
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* @notify_base: pci transport device notify register block base
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* @device: pci transport device device-specific register block base
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* @device_len: pci transport device device-specific register block length
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* @notify_offset_multiplier: multiply queue_notify_off by this value
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*/
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struct virtio_pci_priv {
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struct virtio_pci_common_cfg __iomem *common;
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void __iomem *notify_base;
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void __iomem *device;
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u32 device_len;
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u32 notify_offset_multiplier;
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};
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static int virtio_pci_get_config(struct udevice *udev, unsigned int offset,
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void *buf, unsigned int len)
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{
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struct virtio_pci_priv *priv = dev_get_priv(udev);
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u8 b;
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__le16 w;
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__le32 l;
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WARN_ON(offset + len > priv->device_len);
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switch (len) {
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case 1:
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b = ioread8(priv->device + offset);
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memcpy(buf, &b, sizeof(b));
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break;
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case 2:
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w = cpu_to_le16(ioread16(priv->device + offset));
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memcpy(buf, &w, sizeof(w));
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break;
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case 4:
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l = cpu_to_le32(ioread32(priv->device + offset));
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memcpy(buf, &l, sizeof(l));
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break;
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case 8:
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l = cpu_to_le32(ioread32(priv->device + offset));
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memcpy(buf, &l, sizeof(l));
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l = cpu_to_le32(ioread32(priv->device + offset + sizeof(l)));
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memcpy(buf + sizeof(l), &l, sizeof(l));
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break;
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default:
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WARN_ON(true);
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}
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return 0;
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}
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static int virtio_pci_set_config(struct udevice *udev, unsigned int offset,
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const void *buf, unsigned int len)
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{
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struct virtio_pci_priv *priv = dev_get_priv(udev);
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u8 b;
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__le16 w;
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__le32 l;
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WARN_ON(offset + len > priv->device_len);
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switch (len) {
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case 1:
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memcpy(&b, buf, sizeof(b));
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iowrite8(b, priv->device + offset);
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break;
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case 2:
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memcpy(&w, buf, sizeof(w));
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iowrite16(le16_to_cpu(w), priv->device + offset);
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break;
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case 4:
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memcpy(&l, buf, sizeof(l));
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iowrite32(le32_to_cpu(l), priv->device + offset);
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break;
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case 8:
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memcpy(&l, buf, sizeof(l));
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iowrite32(le32_to_cpu(l), priv->device + offset);
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memcpy(&l, buf + sizeof(l), sizeof(l));
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iowrite32(le32_to_cpu(l), priv->device + offset + sizeof(l));
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break;
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default:
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WARN_ON(true);
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}
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return 0;
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}
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static int virtio_pci_generation(struct udevice *udev, u32 *counter)
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{
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struct virtio_pci_priv *priv = dev_get_priv(udev);
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*counter = ioread8(&priv->common->config_generation);
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return 0;
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}
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static int virtio_pci_get_status(struct udevice *udev, u8 *status)
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{
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struct virtio_pci_priv *priv = dev_get_priv(udev);
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*status = ioread8(&priv->common->device_status);
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return 0;
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}
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static int virtio_pci_set_status(struct udevice *udev, u8 status)
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{
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struct virtio_pci_priv *priv = dev_get_priv(udev);
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/* We should never be setting status to 0 */
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WARN_ON(status == 0);
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iowrite8(status, &priv->common->device_status);
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return 0;
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}
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static int virtio_pci_reset(struct udevice *udev)
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{
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struct virtio_pci_priv *priv = dev_get_priv(udev);
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/* 0 status means a reset */
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iowrite8(0, &priv->common->device_status);
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/*
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* After writing 0 to device_status, the driver MUST wait for a read
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* of device_status to return 0 before reinitializing the device.
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* This will flush out the status write, and flush in device writes,
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* including MSI-X interrupts, if any.
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*/
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while (ioread8(&priv->common->device_status))
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udelay(1000);
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return 0;
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}
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static int virtio_pci_get_features(struct udevice *udev, u64 *features)
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{
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struct virtio_pci_priv *priv = dev_get_priv(udev);
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iowrite32(0, &priv->common->device_feature_select);
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*features = ioread32(&priv->common->device_feature);
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iowrite32(1, &priv->common->device_feature_select);
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*features |= ((u64)ioread32(&priv->common->device_feature) << 32);
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return 0;
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}
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static int virtio_pci_set_features(struct udevice *udev)
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{
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struct virtio_pci_priv *priv = dev_get_priv(udev);
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struct virtio_dev_priv *uc_priv = dev_get_uclass_priv(udev);
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if (!__virtio_test_bit(udev, VIRTIO_F_VERSION_1)) {
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debug("virtio: device uses modern interface but does not have VIRTIO_F_VERSION_1\n");
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return -EINVAL;
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}
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iowrite32(0, &priv->common->guest_feature_select);
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iowrite32((u32)uc_priv->features, &priv->common->guest_feature);
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iowrite32(1, &priv->common->guest_feature_select);
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iowrite32(uc_priv->features >> 32, &priv->common->guest_feature);
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return 0;
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}
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static struct virtqueue *virtio_pci_setup_vq(struct udevice *udev,
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unsigned int index)
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{
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struct virtio_pci_priv *priv = dev_get_priv(udev);
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struct virtio_pci_common_cfg __iomem *cfg = priv->common;
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struct virtqueue *vq;
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u16 num;
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u64 addr;
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int err;
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if (index >= ioread16(&cfg->num_queues))
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return ERR_PTR(-ENOENT);
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/* Select the queue we're interested in */
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iowrite16(index, &cfg->queue_select);
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/* Check if queue is either not available or already active */
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num = ioread16(&cfg->queue_size);
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if (!num || ioread16(&cfg->queue_enable))
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return ERR_PTR(-ENOENT);
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if (num & (num - 1)) {
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printf("(%s): bad queue size %u", udev->name, num);
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return ERR_PTR(-EINVAL);
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}
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/* Create the vring */
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vq = vring_create_virtqueue(index, num, VIRTIO_PCI_VRING_ALIGN, udev);
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if (!vq) {
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err = -ENOMEM;
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goto error_available;
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}
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/* Activate the queue */
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iowrite16(virtqueue_get_vring_size(vq), &cfg->queue_size);
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addr = virtqueue_get_desc_addr(vq);
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iowrite32((u32)addr, &cfg->queue_desc_lo);
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iowrite32(addr >> 32, &cfg->queue_desc_hi);
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addr = virtqueue_get_avail_addr(vq);
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iowrite32((u32)addr, &cfg->queue_avail_lo);
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iowrite32(addr >> 32, &cfg->queue_avail_hi);
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addr = virtqueue_get_used_addr(vq);
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iowrite32((u32)addr, &cfg->queue_used_lo);
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iowrite32(addr >> 32, &cfg->queue_used_hi);
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iowrite16(1, &cfg->queue_enable);
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return vq;
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error_available:
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return ERR_PTR(err);
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}
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static void virtio_pci_del_vq(struct virtqueue *vq)
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{
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struct virtio_pci_priv *priv = dev_get_priv(vq->vdev);
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unsigned int index = vq->index;
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iowrite16(index, &priv->common->queue_select);
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/* Select and deactivate the queue */
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iowrite16(0, &priv->common->queue_enable);
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vring_del_virtqueue(vq);
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}
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static int virtio_pci_del_vqs(struct udevice *udev)
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{
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struct virtio_dev_priv *uc_priv = dev_get_uclass_priv(udev);
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struct virtqueue *vq, *n;
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list_for_each_entry_safe(vq, n, &uc_priv->vqs, list)
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virtio_pci_del_vq(vq);
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return 0;
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}
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static int virtio_pci_find_vqs(struct udevice *udev, unsigned int nvqs,
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struct virtqueue *vqs[])
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{
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int i;
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for (i = 0; i < nvqs; ++i) {
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vqs[i] = virtio_pci_setup_vq(udev, i);
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if (IS_ERR(vqs[i])) {
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virtio_pci_del_vqs(udev);
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return PTR_ERR(vqs[i]);
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}
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}
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return 0;
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}
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static int virtio_pci_notify(struct udevice *udev, struct virtqueue *vq)
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{
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struct virtio_pci_priv *priv = dev_get_priv(udev);
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u16 off;
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/* Select the queue we're interested in */
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iowrite16(vq->index, &priv->common->queue_select);
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/* get offset of notification word for this vq */
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off = ioread16(&priv->common->queue_notify_off);
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/*
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* We write the queue's selector into the notification register
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* to signal the other end
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*/
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iowrite16(vq->index,
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priv->notify_base + off * priv->notify_offset_multiplier);
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return 0;
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}
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/**
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* virtio_pci_find_capability - walk capabilities to find device info
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*
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* @udev: the transport device
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* @cfg_type: the VIRTIO_PCI_CAP_* value we seek
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*
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* @return offset of the configuration structure
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*/
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static int virtio_pci_find_capability(struct udevice *udev, u8 cfg_type)
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{
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int pos;
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int offset;
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u8 type, bar;
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for (pos = dm_pci_find_capability(udev, PCI_CAP_ID_VNDR);
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pos > 0;
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pos = dm_pci_find_next_capability(udev, pos, PCI_CAP_ID_VNDR)) {
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offset = pos + offsetof(struct virtio_pci_cap, cfg_type);
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dm_pci_read_config8(udev, offset, &type);
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offset = pos + offsetof(struct virtio_pci_cap, bar);
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dm_pci_read_config8(udev, offset, &bar);
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/* Ignore structures with reserved BAR values */
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if (bar > 0x5)
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continue;
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if (type == cfg_type)
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return pos;
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}
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return 0;
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}
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/**
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* virtio_pci_map_capability - map base address of the capability
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*
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* @udev: the transport device
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* @off: offset of the configuration structure
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*
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* @return base address of the capability
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*/
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static void __iomem *virtio_pci_map_capability(struct udevice *udev, int off)
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{
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u8 bar;
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u32 offset;
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ulong base;
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void __iomem *p;
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if (!off)
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return NULL;
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offset = off + offsetof(struct virtio_pci_cap, bar);
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dm_pci_read_config8(udev, offset, &bar);
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offset = off + offsetof(struct virtio_pci_cap, offset);
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dm_pci_read_config32(udev, offset, &offset);
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/*
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* TODO: adding 64-bit BAR support
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*
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* Per spec, the BAR is permitted to be either 32-bit or 64-bit.
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* For simplicity, only read the BAR address as 32-bit.
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*/
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base = dm_pci_read_bar32(udev, bar);
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p = (void __iomem *)base + offset;
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return p;
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}
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static int virtio_pci_bind(struct udevice *udev)
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{
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static int num_devs;
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char name[20];
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/* Create a unique device name */
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sprintf(name, "%s#%u", VIRTIO_PCI_DRV_NAME, num_devs++);
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device_set_name(udev, name);
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return 0;
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}
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static int virtio_pci_probe(struct udevice *udev)
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{
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struct pci_child_platdata *pplat = dev_get_parent_platdata(udev);
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struct virtio_dev_priv *uc_priv = dev_get_uclass_priv(udev);
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struct virtio_pci_priv *priv = dev_get_priv(udev);
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u16 subvendor;
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u8 revision;
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int common, notify, device;
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int offset;
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/* We only own devices >= 0x1040 and <= 0x107f: leave the rest. */
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if (pplat->device < 0x1040 || pplat->device > 0x107f)
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return -ENODEV;
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/* Transitional devices must not have a PCI revision ID of 0 */
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dm_pci_read_config8(udev, PCI_REVISION_ID, &revision);
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/* Modern devices: simply use PCI device id, but start from 0x1040. */
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uc_priv->device = pplat->device - 0x1040;
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dm_pci_read_config16(udev, PCI_SUBSYSTEM_VENDOR_ID, &subvendor);
|
|
uc_priv->vendor = subvendor;
|
|
|
|
/* Check for a common config: if not, use legacy mode (bar 0) */
|
|
common = virtio_pci_find_capability(udev, VIRTIO_PCI_CAP_COMMON_CFG);
|
|
if (!common) {
|
|
printf("(%s): leaving for legacy driver\n", udev->name);
|
|
return -ENODEV;
|
|
}
|
|
|
|
/* If common is there, notify should be too */
|
|
notify = virtio_pci_find_capability(udev, VIRTIO_PCI_CAP_NOTIFY_CFG);
|
|
if (!notify) {
|
|
printf("(%s): missing capabilities %i/%i\n", udev->name,
|
|
common, notify);
|
|
return -EINVAL;
|
|
}
|
|
|
|
/*
|
|
* Device capability is only mandatory for devices that have
|
|
* device-specific configuration.
|
|
*/
|
|
device = virtio_pci_find_capability(udev, VIRTIO_PCI_CAP_DEVICE_CFG);
|
|
if (device) {
|
|
offset = notify + offsetof(struct virtio_pci_cap, length);
|
|
dm_pci_read_config32(udev, offset, &priv->device_len);
|
|
}
|
|
|
|
/* Map configuration structures */
|
|
priv->common = virtio_pci_map_capability(udev, common);
|
|
priv->notify_base = virtio_pci_map_capability(udev, notify);
|
|
priv->device = virtio_pci_map_capability(udev, device);
|
|
debug("(%p): common @ %p, notify base @ %p, device @ %p\n",
|
|
udev, priv->common, priv->notify_base, priv->device);
|
|
|
|
/* Read notify_off_multiplier from config space */
|
|
offset = notify + offsetof(struct virtio_pci_notify_cap,
|
|
notify_off_multiplier);
|
|
dm_pci_read_config32(udev, offset, &priv->notify_offset_multiplier);
|
|
|
|
debug("(%s): device (%d) vendor (%08x) version (%d)\n", udev->name,
|
|
uc_priv->device, uc_priv->vendor, revision);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct dm_virtio_ops virtio_pci_ops = {
|
|
.get_config = virtio_pci_get_config,
|
|
.set_config = virtio_pci_set_config,
|
|
.generation = virtio_pci_generation,
|
|
.get_status = virtio_pci_get_status,
|
|
.set_status = virtio_pci_set_status,
|
|
.reset = virtio_pci_reset,
|
|
.get_features = virtio_pci_get_features,
|
|
.set_features = virtio_pci_set_features,
|
|
.find_vqs = virtio_pci_find_vqs,
|
|
.del_vqs = virtio_pci_del_vqs,
|
|
.notify = virtio_pci_notify,
|
|
};
|
|
|
|
U_BOOT_DRIVER(virtio_pci_modern) = {
|
|
.name = VIRTIO_PCI_DRV_NAME,
|
|
.id = UCLASS_VIRTIO,
|
|
.ops = &virtio_pci_ops,
|
|
.bind = virtio_pci_bind,
|
|
.probe = virtio_pci_probe,
|
|
.priv_auto_alloc_size = sizeof(struct virtio_pci_priv),
|
|
};
|
|
|
|
static struct pci_device_id virtio_pci_supported[] = {
|
|
{ PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID00) },
|
|
{ PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID01) },
|
|
{ PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID02) },
|
|
{ PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID03) },
|
|
{ PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID04) },
|
|
{ PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID05) },
|
|
{ PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID06) },
|
|
{ PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID07) },
|
|
{ PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID08) },
|
|
{ PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID09) },
|
|
{ PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID0A) },
|
|
{ PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID0B) },
|
|
{ PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID0C) },
|
|
{ PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID0D) },
|
|
{ PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID0E) },
|
|
{ PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID0F) },
|
|
{ PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID10) },
|
|
{ PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID11) },
|
|
{ PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID12) },
|
|
{ PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID13) },
|
|
{ PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID14) },
|
|
{ PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID15) },
|
|
{ PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID16) },
|
|
{ PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID17) },
|
|
{ PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID18) },
|
|
{ PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID19) },
|
|
{ PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID1A) },
|
|
{ PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID1B) },
|
|
{ PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID1C) },
|
|
{ PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID1D) },
|
|
{ PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID1E) },
|
|
{ PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID1F) },
|
|
{ PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID20) },
|
|
{ PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID21) },
|
|
{ PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID22) },
|
|
{ PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID23) },
|
|
{ PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID24) },
|
|
{ PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID25) },
|
|
{ PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID26) },
|
|
{ PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID27) },
|
|
{ PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID28) },
|
|
{ PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID29) },
|
|
{ PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID2A) },
|
|
{ PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID2B) },
|
|
{ PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID2C) },
|
|
{ PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID2D) },
|
|
{ PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID2E) },
|
|
{ PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID2F) },
|
|
{ PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID30) },
|
|
{ PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID31) },
|
|
{ PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID32) },
|
|
{ PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID33) },
|
|
{ PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID34) },
|
|
{ PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID35) },
|
|
{ PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID36) },
|
|
{ PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID37) },
|
|
{ PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID38) },
|
|
{ PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID39) },
|
|
{ PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID3A) },
|
|
{ PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID3B) },
|
|
{ PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID3C) },
|
|
{ PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID3D) },
|
|
{ PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID3E) },
|
|
{ PCI_DEVICE(VIRTIO_PCI_VENDOR_ID, VIRTIO_PCI_DEVICE_ID3F) },
|
|
{},
|
|
};
|
|
|
|
U_BOOT_PCI_DEVICE(virtio_pci_modern, virtio_pci_supported);
|