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https://github.com/brain-hackers/u-boot-brain
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![Eugeniy Paltsev](/assets/img/avatar_default.png)
As we've dropped NAND support for AXS101 and AXS103
see commit 4f5e552d95
("ARC: AXS10x: drop NAND support")
we don't need bounce buffer anymore.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
192 lines
3.7 KiB
Plaintext
192 lines
3.7 KiB
Plaintext
menu "ARC architecture"
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depends on ARC
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config SYS_ARCH
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default "arc"
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config SYS_CPU
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default "arcv1" if ISA_ARCOMPACT
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default "arcv2" if ISA_ARCV2
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choice
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prompt "ARC Instruction Set"
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default ISA_ARCOMPACT
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config ISA_ARCOMPACT
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bool "ARCompact ISA"
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help
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The original ARC ISA of ARC600/700 cores
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config ISA_ARCV2
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bool "ARC ISA v2"
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help
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ISA for the Next Generation ARC-HS cores
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endchoice
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choice
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prompt "CPU selection"
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default CPU_ARC770D if ISA_ARCOMPACT
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default CPU_ARCHS38 if ISA_ARCV2
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config CPU_ARC750D
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bool "ARC 750D"
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depends on ISA_ARCOMPACT
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select ARC_MMU_V2
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help
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Choose this option to build an U-Boot for ARC750D CPU.
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config CPU_ARC770D
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bool "ARC 770D"
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depends on ISA_ARCOMPACT
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select ARC_MMU_V3
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help
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Choose this option to build an U-Boot for ARC770D CPU.
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config CPU_ARCEM6
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bool "ARC EM6"
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depends on ISA_ARCV2
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select ARC_MMU_ABSENT
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help
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Next Generation ARC Core based on ISA-v2 ISA without MMU.
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config CPU_ARCHS36
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bool "ARC HS36"
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depends on ISA_ARCV2
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select ARC_MMU_ABSENT
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help
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Next Generation ARC Core based on ISA-v2 ISA without MMU.
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config CPU_ARCHS38
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bool "ARC HS38"
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depends on ISA_ARCV2
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select ARC_MMU_V4
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help
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Next Generation ARC Core based on ISA-v2 ISA with MMU.
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endchoice
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choice
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prompt "MMU Version"
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default ARC_MMU_V3 if CPU_ARC770D
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default ARC_MMU_V2 if CPU_ARC750D
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default ARC_MMU_ABSENT if CPU_ARCEM6
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default ARC_MMU_ABSENT if CPU_ARCHS36
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default ARC_MMU_V4 if CPU_ARCHS38
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config ARC_MMU_ABSENT
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bool "No MMU"
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help
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No MMU
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config ARC_MMU_V2
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bool "MMU v2"
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depends on CPU_ARC750D
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help
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Fixed the deficiency of v1 - possible thrashing in memcpy sceanrio
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when 2 D-TLB and 1 I-TLB entries index into same 2way set.
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config ARC_MMU_V3
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bool "MMU v3"
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depends on CPU_ARC770D
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help
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Introduced with ARC700 4.10: New Features
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Variable Page size (1k-16k), var JTLB size 128 x (2 or 4)
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Shared Address Spaces (SASID)
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config ARC_MMU_V4
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bool "MMU v4"
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depends on CPU_ARCHS38
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help
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Introduced as a part of ARC HS38 release.
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endchoice
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config CPU_BIG_ENDIAN
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bool "Enable Big Endian Mode"
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default n
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help
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Build kernel for Big Endian Mode of ARC CPU
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config SYS_ICACHE_OFF
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bool "Do not enable icache"
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default n
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help
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Do not enable instruction cache in U-Boot.
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config SPL_SYS_ICACHE_OFF
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bool "Do not enable icache in SPL"
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depends on SPL
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default SYS_ICACHE_OFF
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help
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Do not enable instruction cache in SPL.
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config SYS_DCACHE_OFF
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bool "Do not enable dcache"
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default n
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help
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Do not enable data cache in U-Boot.
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config SPL_SYS_DCACHE_OFF
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bool "Do not enable dcache in SPL"
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depends on SPL
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default SYS_DCACHE_OFF
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help
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Do not enable data cache in SPL.
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menuconfig ARC_DBG
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bool "ARC debugging"
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default n
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if ARC_DBG
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config ARC_DBG_IOC_ENABLE
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bool "Enable IO coherency unit"
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depends on CPU_ARCHS38
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default n
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help
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Enable IO coherency unit to debug problems with caches and
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DMA peripherals.
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NOTE: as of today linux will not work properly if this option
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is enabled in u-boot!
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endif
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choice
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prompt "Target select"
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default TARGET_AXS103
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config TARGET_TB100
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bool "Support tb100"
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config TARGET_NSIM
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bool "Support ARC simulation & prototyping platforms"
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config TARGET_AXS101
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bool "Support Synopsys Designware SDP board AXS101"
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config TARGET_AXS103
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bool "Support Synopsys Designware SDP board AXS103"
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config TARGET_EMSDP
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bool "Synopsys EM Software Development Platform"
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select CPU_ARCEM6
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config TARGET_HSDK
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bool "Support Synopsys HSDK or HSDK-4xD board"
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config TARGET_IOT_DEVKIT
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bool "Synopsys Brite IoT Development kit"
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select CPU_ARCEM6
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endchoice
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source "board/abilis/tb100/Kconfig"
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source "board/synopsys/axs10x/Kconfig"
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source "board/synopsys/emsdp/Kconfig"
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source "board/synopsys/hsdk/Kconfig"
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source "board/synopsys/iot_devkit/Kconfig"
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source "board/synopsys/nsim/Kconfig"
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endmenu
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