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https://github.com/brain-hackers/u-boot-brain
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82b7725b6d
The P1020/P1011 SOCs support max 32bit DDR width as opposed to P2020/P2010 where max DDR data width supported is 64bit. As a next step the DDR data width initialization would be made more dynamic with more flexibility from the board perspective and user choice. Going forward we would also remove the hardcodings for platforms with onboard memories and try to use the FSL SPD code for DDR initialization. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
258 lines
9.3 KiB
C
258 lines
9.3 KiB
C
/*
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* Copyright 2009 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/mmu.h>
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#include <asm/immap_85xx.h>
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#include <asm/processor.h>
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#include <asm/fsl_ddr_sdram.h>
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#include <asm/io.h>
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#include <asm/fsl_law.h>
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DECLARE_GLOBAL_DATA_PTR;
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extern void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
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unsigned int ctrl_num);
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#define DATARATE_400MHZ 400000000
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#define DATARATE_533MHZ 533333333
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#define DATARATE_667MHZ 666666666
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#define DATARATE_800MHZ 800000000
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#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F
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#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
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#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
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#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
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#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
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#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
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#define CONFIG_SYS_DDR_ZQ_CONTROL 0x00000000
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#define CONFIG_SYS_DDR_WRLVL_CONTROL 0x00000000
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#define CONFIG_SYS_DDR_SR_CNTR 0x00000000
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#define CONFIG_SYS_DDR_RCW_1 0x00000000
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#define CONFIG_SYS_DDR_RCW_2 0x00000000
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#define CONFIG_SYS_DDR_CONTROL 0x43000000 /* Type = DDR2*/
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#define CONFIG_SYS_DDR_CONTROL_2 0x24401000
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#define CONFIG_SYS_DDR_TIMING_4 0x00000000
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#define CONFIG_SYS_DDR_TIMING_5 0x00000000
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#define CONFIG_SYS_DDR_TIMING_3_400 0x00010000
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#define CONFIG_SYS_DDR_TIMING_0_400 0x00260802
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#define CONFIG_SYS_DDR_TIMING_1_400 0x39355322
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#define CONFIG_SYS_DDR_TIMING_2_400 0x1f9048ca
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#define CONFIG_SYS_DDR_CLK_CTRL_400 0x02800000
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#define CONFIG_SYS_DDR_MODE_1_400 0x00480432
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#define CONFIG_SYS_DDR_MODE_2_400 0x00000000
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#define CONFIG_SYS_DDR_INTERVAL_400 0x06180100
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#define CONFIG_SYS_DDR_TIMING_3_533 0x00020000
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#define CONFIG_SYS_DDR_TIMING_0_533 0x00260802
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#define CONFIG_SYS_DDR_TIMING_1_533 0x4c47c432
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#define CONFIG_SYS_DDR_TIMING_2_533 0x0f9848ce
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#define CONFIG_SYS_DDR_CLK_CTRL_533 0x02800000
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#define CONFIG_SYS_DDR_MODE_1_533 0x00040642
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#define CONFIG_SYS_DDR_MODE_2_533 0x00000000
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#define CONFIG_SYS_DDR_INTERVAL_533 0x08200100
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#define CONFIG_SYS_DDR_TIMING_3_667 0x00030000
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#define CONFIG_SYS_DDR_TIMING_0_667 0x55770802
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#define CONFIG_SYS_DDR_TIMING_1_667 0x5f599543
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#define CONFIG_SYS_DDR_TIMING_2_667 0x0fa074d1
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#define CONFIG_SYS_DDR_CLK_CTRL_667 0x02800000
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#define CONFIG_SYS_DDR_MODE_1_667 0x00040852
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#define CONFIG_SYS_DDR_MODE_2_667 0x00000000
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#define CONFIG_SYS_DDR_INTERVAL_667 0x0a280100
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#define CONFIG_SYS_DDR_TIMING_3_800 0x00040000
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#define CONFIG_SYS_DDR_TIMING_0_800 0x55770802
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#define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b6543
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#define CONFIG_SYS_DDR_TIMING_2_800 0x0fa074d1
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#define CONFIG_SYS_DDR_CLK_CTRL_800 0x02000000
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#define CONFIG_SYS_DDR_MODE_1_800 0x00440862
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#define CONFIG_SYS_DDR_MODE_2_800 0x00000000
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#define CONFIG_SYS_DDR_INTERVAL_800 0x0a280100
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fsl_ddr_cfg_regs_t ddr_cfg_regs_400 = {
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.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
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.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
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.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
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.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_400,
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.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_400,
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.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_400,
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.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_400,
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.ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
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.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
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.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_400,
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.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_400,
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.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
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.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_400,
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.ddr_data_init = CONFIG_MEM_INIT_VALUE,
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.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_400,
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.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
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.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
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.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
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.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
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.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
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.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
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.ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
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.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
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.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
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};
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fsl_ddr_cfg_regs_t ddr_cfg_regs_533 = {
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.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
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.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
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.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
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.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_533,
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.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_533,
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.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_533,
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.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_533,
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.ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
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.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
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.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_533,
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.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_533,
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.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
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.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_533,
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.ddr_data_init = CONFIG_MEM_INIT_VALUE,
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.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_533,
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.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
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.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
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.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
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.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
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.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
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.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
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.ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
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.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
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.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
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};
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fsl_ddr_cfg_regs_t ddr_cfg_regs_667 = {
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.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
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.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
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.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
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.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_667,
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.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_667,
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.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_667,
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.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_667,
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.ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
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.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
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.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_667,
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.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_667,
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.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
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.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_667,
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.ddr_data_init = CONFIG_MEM_INIT_VALUE,
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.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_667,
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.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
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.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
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.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
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.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
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.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
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.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
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.ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
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.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
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.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
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};
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fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = {
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.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
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.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
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.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
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.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3_800,
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.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0_800,
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.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800,
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.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_800,
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.ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
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.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
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.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1_800,
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.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2_800,
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.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
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.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL_800,
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.ddr_data_init = CONFIG_MEM_INIT_VALUE,
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.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL_800,
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.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
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.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
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.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
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.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
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.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
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.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
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.ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
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.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
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.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
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};
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/*
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* Fixed sdram init -- doesn't use serial presence detect.
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*/
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phys_size_t fixed_sdram (void)
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{
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sys_info_t sysinfo;
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char buf[32];
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fsl_ddr_cfg_regs_t *ddr_cfg_regs = NULL;
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size_t ddr_size;
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struct cpu_type *cpu;
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get_sys_info(&sysinfo);
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printf("Configuring DDR for %s MT/s data rate\n",
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strmhz(buf, sysinfo.freqDDRBus));
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if(sysinfo.freqDDRBus <= DATARATE_400MHZ)
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ddr_cfg_regs = &ddr_cfg_regs_400;
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else if(sysinfo.freqDDRBus <= DATARATE_533MHZ)
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ddr_cfg_regs = &ddr_cfg_regs_533;
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else if(sysinfo.freqDDRBus <= DATARATE_667MHZ)
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ddr_cfg_regs = &ddr_cfg_regs_667;
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else if(sysinfo.freqDDRBus <= DATARATE_800MHZ)
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ddr_cfg_regs = &ddr_cfg_regs_800;
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else
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panic("Unsupported DDR data rate %s MT/s data rate\n",
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strmhz(buf, sysinfo.freqDDRBus));
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cpu = gd->cpu;
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/* P1020 and it's derivatives support max 32bit DDR width */
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if(cpu->soc_ver == SVR_P1020 || cpu->soc_ver == SVR_P1020_E ||
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cpu->soc_ver == SVR_P1011 || cpu->soc_ver == SVR_P1011_E) {
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ddr_cfg_regs->ddr_sdram_cfg |= SDRAM_CFG_32_BE;
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ddr_cfg_regs->cs[0].bnds = 0x0000001F;
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ddr_size = (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024 / 2);
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}
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else
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ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
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fsl_ddr_set_memctl_regs(ddr_cfg_regs, 0);
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return ddr_size;
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}
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phys_size_t initdram(int board_type)
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{
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phys_size_t dram_size = 0;
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dram_size = fixed_sdram();
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set_ddr_laws(0, dram_size, LAW_TRGT_IF_DDR_1);
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dram_size = setup_ddr_tlbs(dram_size / 0x100000);
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dram_size *= 0x100000;
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puts("DDR: ");
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return dram_size;
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}
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