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https://github.com/brain-hackers/u-boot-brain
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83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
94 lines
4.5 KiB
C
94 lines
4.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2003 Arabella Software Ltd.
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* Yuli Barcohen <yuli@arabellasw.com>
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*
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* Serial Presence Detect (SPD) EEPROM format according to the
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* Intel's PC SDRAM Serial Presence Detect (SPD) Specification,
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* revision 1.2B, November 1999
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*/
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#ifndef _SPD_H_
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#define _SPD_H_
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typedef struct spd_eeprom_s {
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unsigned char info_size; /* 0 # bytes written into serial memory */
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unsigned char chip_size; /* 1 Total # bytes of SPD memory device */
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unsigned char mem_type; /* 2 Fundamental memory type */
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unsigned char nrow_addr; /* 3 # of Row Addresses on this assembly */
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unsigned char ncol_addr; /* 4 # of Column Addrs on this assembly */
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unsigned char nrows; /* 5 # of Module Rows on this assembly */
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unsigned char dataw_lsb; /* 6 Data Width of this assembly */
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unsigned char dataw_msb; /* 7 ... Data Width continuation */
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unsigned char voltage; /* 8 Voltage intf std of this assembly */
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unsigned char clk_cycle; /* 9 SDRAM Cycle time at CL=X */
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unsigned char clk_access; /* 10 SDRAM Access from Clock at CL=X */
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unsigned char config; /* 11 DIMM Configuration type */
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unsigned char refresh; /* 12 Refresh Rate/Type */
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unsigned char primw; /* 13 Primary SDRAM Width */
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unsigned char ecw; /* 14 Error Checking SDRAM width */
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unsigned char min_delay; /* 15 for Back to Back Random Address */
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unsigned char burstl; /* 16 Burst Lengths Supported */
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unsigned char nbanks; /* 17 # of Banks on Each SDRAM Device */
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unsigned char cas_lat; /* 18 CAS# Latencies Supported */
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unsigned char cs_lat; /* 19 CS# Latency */
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unsigned char write_lat; /* 20 Write Latency (aka Write Recovery) */
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unsigned char mod_attr; /* 21 SDRAM Module Attributes */
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unsigned char dev_attr; /* 22 SDRAM Device Attributes */
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unsigned char clk_cycle2; /* 23 Min SDRAM Cycle time at CL=X-1 */
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unsigned char clk_access2; /* 24 SDRAM Access from Clock at CL=X-1 */
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unsigned char clk_cycle3; /* 25 Min SDRAM Cycle time at CL=X-2 */
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unsigned char clk_access3; /* 26 Max Access from Clock at CL=X-2 */
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unsigned char trp; /* 27 Min Row Precharge Time (tRP)*/
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unsigned char trrd; /* 28 Min Row Active to Row Active (tRRD) */
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unsigned char trcd; /* 29 Min RAS to CAS Delay (tRCD) */
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unsigned char tras; /* 30 Minimum RAS Pulse Width (tRAS) */
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unsigned char row_dens; /* 31 Density of each row on module */
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unsigned char ca_setup; /* 32 Cmd + Addr signal input setup time */
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unsigned char ca_hold; /* 33 Cmd and Addr signal input hold time */
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unsigned char data_setup; /* 34 Data signal input setup time */
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unsigned char data_hold; /* 35 Data signal input hold time */
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unsigned char twr; /* 36 Write Recovery time tWR */
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unsigned char twtr; /* 37 Int write to read delay tWTR */
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unsigned char trtp; /* 38 Int read to precharge delay tRTP */
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unsigned char mem_probe; /* 39 Mem analysis probe characteristics */
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unsigned char trctrfc_ext; /* 40 Extensions to trc and trfc */
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unsigned char trc; /* 41 Min Active to Auto refresh time tRC */
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unsigned char trfc; /* 42 Min Auto to Active period tRFC */
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unsigned char tckmax; /* 43 Max device cycle time tCKmax */
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unsigned char tdqsq; /* 44 Max DQS to DQ skew */
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unsigned char tqhs; /* 45 Max Read DataHold skew tQHS */
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unsigned char pll_relock; /* 46 PLL Relock time */
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unsigned char res[15]; /* 47-xx IDD in SPD and Reserved space */
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unsigned char spd_rev; /* 62 SPD Data Revision Code */
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unsigned char cksum; /* 63 Checksum for bytes 0-62 */
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unsigned char mid[8]; /* 64 Mfr's JEDEC ID code per JEP-108E */
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unsigned char mloc; /* 72 Manufacturing Location */
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unsigned char mpart[18]; /* 73 Manufacturer's Part Number */
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unsigned char rev[2]; /* 91 Revision Code */
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unsigned char mdate[2]; /* 93 Manufacturing Date */
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unsigned char sernum[4]; /* 95 Assembly Serial Number */
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unsigned char mspec[27]; /* 99 Manufacturer Specific Data */
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/*
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* Open for Customer Use starting with byte 128.
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*/
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unsigned char freq; /* 128 Intel spec: frequency */
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unsigned char intel_cas; /* 129 Intel spec: CAS# Latency support */
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} spd_eeprom_t;
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/*
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* Byte 2 Fundamental Memory Types.
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*/
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#define SPD_MEMTYPE_FPM (0x01)
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#define SPD_MEMTYPE_EDO (0x02)
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#define SPD_MEMTYPE_PIPE_NIBBLE (0x03)
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#define SPD_MEMTYPE_SDRAM (0x04)
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#define SPD_MEMTYPE_ROM (0x05)
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#define SPD_MEMTYPE_SGRAM (0x06)
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#define SPD_MEMTYPE_DDR (0x07)
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#define SPD_MEMTYPE_DDR2 (0x08)
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#endif /* _SPD_H_ */
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