mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
70 lines
2.4 KiB
C
70 lines
2.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2011
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* Marvell Inc, <www.marvell.com>
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*/
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#ifndef _MV_I2C_H_
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#define _MV_I2C_H_
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extern void i2c_clk_enable(void);
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/* Shall the current transfer have a start/stop condition? */
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#define I2C_COND_NORMAL 0
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#define I2C_COND_START 1
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#define I2C_COND_STOP 2
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/* Shall the current transfer be ack/nacked or being waited for it? */
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#define I2C_ACKNAK_WAITACK 1
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#define I2C_ACKNAK_SENDACK 2
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#define I2C_ACKNAK_SENDNAK 4
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/* Specify who shall transfer the data (master or slave) */
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#define I2C_READ 0
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#define I2C_WRITE 1
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#define I2C_ICR_INIT (ICR_BEIE | ICR_IRFIE | ICR_ITEIE | ICR_GCD | ICR_SCLE)
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#define I2C_ISR_INIT 0x7FF
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/* ----- Control register bits ---------------------------------------- */
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#define ICR_START 0x1 /* start bit */
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#define ICR_STOP 0x2 /* stop bit */
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#define ICR_ACKNAK 0x4 /* send ACK(0) or NAK(1) */
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#define ICR_TB 0x8 /* transfer byte bit */
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#define ICR_MA 0x10 /* master abort */
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#define ICR_SCLE 0x20 /* master clock enable, mona SCLEA */
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#define ICR_IUE 0x40 /* unit enable */
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#define ICR_GCD 0x80 /* general call disable */
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#define ICR_ITEIE 0x100 /* enable tx interrupts */
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#define ICR_IRFIE 0x200 /* enable rx interrupts, mona: DRFIE */
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#define ICR_BEIE 0x400 /* enable bus error ints */
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#define ICR_SSDIE 0x800 /* slave STOP detected int enable */
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#define ICR_ALDIE 0x1000 /* enable arbitration interrupt */
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#define ICR_SADIE 0x2000 /* slave address detected int enable */
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#define ICR_UR 0x4000 /* unit reset */
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#ifdef CONFIG_ARMADA_3700
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#define ICR_SM 0x00000 /* Standard Mode */
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#define ICR_FM 0x10000 /* Fast Mode */
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#define ICR_MODE_MASK 0x30000 /* Mode mask */
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#else
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#define ICR_SM 0x00000 /* Standard Mode */
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#define ICR_FM 0x08000 /* Fast Mode */
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#define ICR_MODE_MASK 0x18000 /* Mode mask */
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#endif
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/* ----- Status register bits ----------------------------------------- */
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#define ISR_RWM 0x1 /* read/write mode */
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#define ISR_ACKNAK 0x2 /* ack/nak status */
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#define ISR_UB 0x4 /* unit busy */
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#define ISR_IBB 0x8 /* bus busy */
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#define ISR_SSD 0x10 /* slave stop detected */
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#define ISR_ALD 0x20 /* arbitration loss detected */
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#define ISR_ITE 0x40 /* tx buffer empty */
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#define ISR_IRF 0x80 /* rx buffer full */
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#define ISR_GCAD 0x100 /* general call address detected */
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#define ISR_SAD 0x200 /* slave address detected */
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#define ISR_BED 0x400 /* bus error no ACK/NAK */
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#endif
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