mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
95e9a8e2cb
Changes in relation to FriendlyARM's U-Boot nanopi2-v2016.01:
- SPL not supported yet --> no spl-directory in arch/arm/mach-nexell.
Appropriate line in Makefile removed.
- clock.c: 'section(".data")' added to declaration of clk_periphs[] and
core_hz.
- Kconfig: Changes to have a structure like in mach-bcm283x/Kconfig,
e.g. "config ..." entries moved from other Kconfig.
- timer.c: 'section(".data")' added to declaration of timestamp and
lastdec.
- arch/arm/mach-nexell/serial.c removed because this is for the UARTs
of the S5P6818 SoC which is not supported yet. S5P4418 UARTs are
different, here the (existing) PL011-code is used.
- '#ifdef CONFIG...' changed to 'if (IS_ENABLED(CONFIG...))' where
possible (and similar).
Signed-off-by: Stefan Bosch <stefan_b@posteo.net>
108 lines
2.5 KiB
C
108 lines
2.5 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2016 Nexell
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* Youngbok, Park <park@nexell.co.kr>
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*/
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#include <common.h>
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#include <asm/arch/nexell.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/reset.h>
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#include <asm/arch/nx_gpio.h>
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#include <asm/arch/tieoff.h>
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#include <asm/arch/sec_reg.h>
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#define NX_PIN_FN_SIZE 4
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#define TIEOFF_REG_NUM 33
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struct nx_tieoff_registerset {
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u32 tieoffreg[TIEOFF_REG_NUM];
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};
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static struct nx_tieoff_registerset *nx_tieoff = (void *)PHY_BASEADDR_TIEOFF;
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static int tieoff_readl(void __iomem *reg)
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{
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if (IS_ENABLED(CONFIG_ARCH_S5P4418))
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return read_sec_reg_by_id(reg, NEXELL_TOFF_SEC_ID);
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else
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return readl(reg);
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}
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static int tieoff_writetl(void __iomem *reg, int val)
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{
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if (IS_ENABLED(CONFIG_ARCH_S5P4418))
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return write_sec_reg_by_id(reg, val, NEXELL_TOFF_SEC_ID);
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else
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return writel(val, reg);
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}
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void nx_tieoff_set(u32 tieoff_index, u32 tieoff_value)
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{
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u32 regindex, mask;
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u32 lsb, msb;
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u32 regval;
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u32 position;
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u32 bitwidth;
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position = tieoff_index & 0xffff;
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bitwidth = (tieoff_index >> 16) & 0xffff;
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regindex = position >> 5;
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lsb = position & 0x1F;
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msb = lsb + bitwidth;
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if (msb > 32) {
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msb &= 0x1F;
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mask = ~(0xffffffff << lsb);
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regval = tieoff_readl(&nx_tieoff->tieoffreg[regindex]) & mask;
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regval |= ((tieoff_value & ((1UL << bitwidth) - 1)) << lsb);
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tieoff_writetl(&nx_tieoff->tieoffreg[regindex], regval);
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mask = (0xffffffff << msb);
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regval = tieoff_readl(&nx_tieoff->tieoffreg[regindex]) & mask;
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regval |= ((tieoff_value & ((1UL << bitwidth) - 1)) >> msb);
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tieoff_writetl(&nx_tieoff->tieoffreg[regindex + 1], regval);
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} else {
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mask = (0xffffffff << msb) | (~(0xffffffff << lsb));
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regval = tieoff_readl(&nx_tieoff->tieoffreg[regindex]) & mask;
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regval |= ((tieoff_value & ((1UL << bitwidth) - 1)) << lsb);
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tieoff_writetl(&nx_tieoff->tieoffreg[regindex], regval);
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}
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}
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u32 nx_tieoff_get(u32 tieoff_index)
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{
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u32 regindex, mask;
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u32 lsb, msb;
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u32 regval;
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u32 position;
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u32 bitwidth;
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position = tieoff_index & 0xffff;
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bitwidth = (tieoff_index >> 16) & 0xffff;
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regindex = position / 32;
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lsb = position % 32;
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msb = lsb + bitwidth;
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if (msb > 32) {
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msb &= 0x1F;
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mask = 0xffffffff << lsb;
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regval = tieoff_readl(&nx_tieoff->tieoffreg[regindex]) & mask;
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regval >>= lsb;
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mask = ~(0xffffffff << msb);
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regval |= ((tieoff_readl(&nx_tieoff->tieoffreg[regindex + 1])
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& mask) << (32 - lsb));
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} else {
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mask = ~(0xffffffff << msb) & (0xffffffff << lsb);
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regval = tieoff_readl(&nx_tieoff->tieoffreg[regindex]) & mask;
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regval >>= lsb;
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}
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return regval;
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}
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