mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 07:16:04 +09:00
7ccaa31380
A previous series already update STMicroelectronics emails maintainers but some files have been omitted (Makefile, .dts, .dtsi and .rst files). Update Patrick and my email address with the one dedicated to upstream activities. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
224 lines
4.8 KiB
Plaintext
224 lines
4.8 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+
|
|
/*
|
|
* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
|
|
* Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics.
|
|
*/
|
|
|
|
#include <dt-bindings/memory/stm32-sdram.h>
|
|
/{
|
|
clocks {
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
|
|
aliases {
|
|
/* Aliases for gpios so as to use sequence */
|
|
gpio0 = &gpioa;
|
|
gpio1 = &gpiob;
|
|
gpio2 = &gpioc;
|
|
gpio3 = &gpiod;
|
|
gpio4 = &gpioe;
|
|
gpio5 = &gpiof;
|
|
gpio6 = &gpiog;
|
|
gpio7 = &gpioh;
|
|
gpio8 = &gpioi;
|
|
gpio9 = &gpioj;
|
|
gpio10 = &gpiok;
|
|
};
|
|
|
|
soc {
|
|
u-boot,dm-pre-reloc;
|
|
pin-controller {
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
|
|
fmc: fmc@A0000000 {
|
|
compatible = "st,stm32-fmc";
|
|
reg = <0xA0000000 0x1000>;
|
|
clocks = <&rcc 0 STM32F4_AHB3_CLOCK(FMC)>;
|
|
st,syscfg = <&syscfg>;
|
|
pinctrl-0 = <&fmc_pins_d32>;
|
|
pinctrl-names = "default";
|
|
st,mem_remap = <4>;
|
|
u-boot,dm-pre-reloc;
|
|
|
|
/*
|
|
* Memory configuration from sdram
|
|
* MICRON MT48LC4M32B2B5-7
|
|
*/
|
|
bank0: bank@0 {
|
|
st,sdram-control = /bits/ 8 <NO_COL_9
|
|
NO_ROW_12
|
|
MWIDTH_32
|
|
BANKS_4
|
|
CAS_3
|
|
SDCLK_2
|
|
RD_BURST_EN
|
|
RD_PIPE_DL_0>;
|
|
st,sdram-timing = /bits/ 8 <TMRD_2
|
|
TXSR_6
|
|
TRAS_4
|
|
TRC_6
|
|
TWR_2
|
|
TRP_2
|
|
TRCD_2>;
|
|
st,sdram-refcount = < 2812 >;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
&clk_hse {
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
|
|
&clk_lse {
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
|
|
&clk_i2s_ckin {
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
|
|
&pwrcfg {
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
|
|
&syscfg {
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
|
|
&rcc {
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
|
|
&gpioa {
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
|
|
&gpiob {
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
|
|
&gpioc {
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
|
|
&gpiod {
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
|
|
&gpioe {
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
|
|
&gpiof {
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
|
|
&gpiog {
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
|
|
&gpioh {
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
|
|
&gpioi {
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
|
|
&gpioj {
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
|
|
&gpiok {
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
|
|
&pinctrl {
|
|
usart1_pins_a: usart1-0 {
|
|
u-boot,dm-pre-reloc;
|
|
pins1 {
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
pins2 {
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
};
|
|
|
|
fmc_pins_d32: fmc_d32@0 {
|
|
u-boot,dm-pre-reloc;
|
|
pins
|
|
{
|
|
pinmux = <STM32_PINMUX('I',10, AF12)>, /* D31 */
|
|
<STM32_PINMUX('I', 9, AF12)>, /* D30 */
|
|
<STM32_PINMUX('I', 7, AF12)>, /* D29 */
|
|
<STM32_PINMUX('I', 6, AF12)>, /* D28 */
|
|
<STM32_PINMUX('I', 3, AF12)>, /* D27 */
|
|
<STM32_PINMUX('I', 2, AF12)>, /* D26 */
|
|
<STM32_PINMUX('I', 1, AF12)>, /* D25 */
|
|
<STM32_PINMUX('I', 0, AF12)>, /* D24 */
|
|
<STM32_PINMUX('H',15, AF12)>, /* D23 */
|
|
<STM32_PINMUX('H',14, AF12)>, /* D22 */
|
|
<STM32_PINMUX('H',13, AF12)>, /* D21 */
|
|
<STM32_PINMUX('H',12, AF12)>, /* D20 */
|
|
<STM32_PINMUX('H',11, AF12)>, /* D19 */
|
|
<STM32_PINMUX('H',10, AF12)>, /* D18 */
|
|
<STM32_PINMUX('H', 9, AF12)>, /* D17 */
|
|
<STM32_PINMUX('H', 8, AF12)>, /* D16 */
|
|
|
|
<STM32_PINMUX('D',10, AF12)>, /* D15 */
|
|
<STM32_PINMUX('D', 9, AF12)>, /* D14 */
|
|
<STM32_PINMUX('D', 8, AF12)>, /* D13 */
|
|
<STM32_PINMUX('E',15, AF12)>, /* D12 */
|
|
<STM32_PINMUX('E',14, AF12)>, /* D11 */
|
|
<STM32_PINMUX('E',13, AF12)>, /* D10 */
|
|
<STM32_PINMUX('E',12, AF12)>, /* D09 */
|
|
<STM32_PINMUX('E',11, AF12)>, /* D08 */
|
|
<STM32_PINMUX('E',10, AF12)>, /* D07 */
|
|
<STM32_PINMUX('E', 9, AF12)>, /* D06 */
|
|
<STM32_PINMUX('E', 8, AF12)>, /* D05 */
|
|
<STM32_PINMUX('E', 7, AF12)>, /* D04 */
|
|
<STM32_PINMUX('D', 1, AF12)>, /* D03 */
|
|
<STM32_PINMUX('D', 0, AF12)>, /* D02 */
|
|
<STM32_PINMUX('D',15, AF12)>, /* D01 */
|
|
<STM32_PINMUX('D',14, AF12)>, /* D00 */
|
|
|
|
<STM32_PINMUX('E', 0, AF12)>, /* NBL0 */
|
|
<STM32_PINMUX('E', 1, AF12)>, /* NBL1 */
|
|
<STM32_PINMUX('I', 4, AF12)>, /* NBL2 */
|
|
<STM32_PINMUX('I', 5, AF12)>, /* NBL3 */
|
|
|
|
<STM32_PINMUX('G', 5, AF12)>, /* A15-BA1 */
|
|
<STM32_PINMUX('G', 4, AF12)>, /* A14-BA0 */
|
|
<STM32_PINMUX('G', 3, AF12)>, /* A13 */
|
|
<STM32_PINMUX('G', 2, AF12)>, /* A12 */
|
|
<STM32_PINMUX('G', 1, AF12)>, /* A11 */
|
|
<STM32_PINMUX('G', 0, AF12)>, /* A10 */
|
|
<STM32_PINMUX('F',15, AF12)>, /* A09 */
|
|
<STM32_PINMUX('F',14, AF12)>, /* A08 */
|
|
<STM32_PINMUX('F',13, AF12)>, /* A07 */
|
|
<STM32_PINMUX('F',12, AF12)>, /* A06 */
|
|
<STM32_PINMUX('F', 5, AF12)>, /* A05 */
|
|
<STM32_PINMUX('F', 4, AF12)>, /* A04 */
|
|
<STM32_PINMUX('F', 3, AF12)>, /* A03 */
|
|
<STM32_PINMUX('F', 2, AF12)>, /* A02 */
|
|
<STM32_PINMUX('F', 1, AF12)>, /* A01 */
|
|
<STM32_PINMUX('F', 0, AF12)>, /* A00 */
|
|
|
|
<STM32_PINMUX('H', 3, AF12)>, /* SDNE0 */
|
|
<STM32_PINMUX('H', 5, AF12)>, /* SDNWE */
|
|
<STM32_PINMUX('F',11, AF12)>, /* SDNRAS */
|
|
<STM32_PINMUX('G',15, AF12)>, /* SDNCAS */
|
|
<STM32_PINMUX('H', 2, AF12)>, /* SDCKE0 */
|
|
<STM32_PINMUX('G', 8, AF12)>; /* SDCLK> */
|
|
slew-rate = <2>;
|
|
u-boot,dm-pre-reloc;
|
|
};
|
|
};
|
|
};
|
|
|
|
&timer5 {
|
|
u-boot,dm-pre-reloc;
|
|
};
|