mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 15:26:03 +09:00
5972c57780
The rng is embedded in the SoC so enable it in the device tree universally, the use of it can be controlled by enabling/disabling at the device config level. Signed-off-by: Peter Robinson <pbrobinson@gmail.com> Cc: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
146 lines
2.2 KiB
Plaintext
146 lines
2.2 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2019 Jagan Teki <jagan@amarulasolutions.com>
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*/
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#define USB_CLASS_HUB 9
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#include "rockchip-u-boot.dtsi"
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/ {
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aliases {
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mmc0 = &sdhci;
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mmc1 = &sdmmc;
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pci0 = &pcie0;
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spi1 = &spi1;
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};
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cic: syscon@ff620000 {
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u-boot,dm-pre-reloc;
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compatible = "rockchip,rk3399-cic", "syscon";
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reg = <0x0 0xff620000 0x0 0x100>;
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};
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dfi: dfi@ff630000 {
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u-boot,dm-pre-reloc;
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reg = <0x00 0xff630000 0x00 0x4000>;
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compatible = "rockchip,rk3399-dfi";
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rockchip,pmu = <&pmugrf>;
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clocks = <&cru PCLK_DDR_MON>;
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clock-names = "pclk_ddr_mon";
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};
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rng: rng@ff8b8000 {
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compatible = "rockchip,cryptov1-rng";
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reg = <0x0 0xff8b8000 0x0 0x1000>;
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status = "okay";
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};
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dmc: dmc {
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u-boot,dm-pre-reloc;
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compatible = "rockchip,rk3399-dmc";
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devfreq-events = <&dfi>;
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interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&cru SCLK_DDRCLK>;
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clock-names = "dmc_clk";
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reg = <0x0 0xffa80000 0x0 0x0800
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0x0 0xffa80800 0x0 0x1800
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0x0 0xffa82000 0x0 0x2000
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0x0 0xffa84000 0x0 0x1000
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0x0 0xffa88000 0x0 0x0800
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0x0 0xffa88800 0x0 0x1800
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0x0 0xffa8a000 0x0 0x2000
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0x0 0xffa8c000 0x0 0x1000>;
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};
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pmusgrf: syscon@ff330000 {
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u-boot,dm-pre-reloc;
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compatible = "rockchip,rk3399-pmusgrf", "syscon";
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reg = <0x0 0xff330000 0x0 0xe3d4>;
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};
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};
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#ifdef CONFIG_ROCKCHIP_SPI_IMAGE
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&binman {
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rom {
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filename = "u-boot.rom";
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size = <0x400000>;
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pad-byte = <0xff>;
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mkimage {
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args = "-n rk3399 -T rkspi";
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u-boot-spl {
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};
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};
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u-boot-img {
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offset = <0x40000>;
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};
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u-boot {
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offset = <0x300000>;
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};
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fdtmap {
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};
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};
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};
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#endif
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&cru {
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u-boot,dm-pre-reloc;
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};
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&grf {
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u-boot,dm-pre-reloc;
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};
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&pinctrl {
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u-boot,dm-pre-reloc;
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};
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&pmu {
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u-boot,dm-pre-reloc;
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};
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&pmugrf {
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u-boot,dm-pre-reloc;
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};
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&pmu {
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u-boot,dm-pre-reloc;
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};
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&pmucru {
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u-boot,dm-pre-reloc;
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};
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&sdhci {
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max-frequency = <200000000>;
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u-boot,dm-pre-reloc;
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};
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&sdmmc {
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u-boot,dm-pre-reloc;
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/* mmc to sram can't do dma, prevent aborts transferring TF-A parts */
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u-boot,spl-fifo-mode;
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};
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&spi1 {
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u-boot,dm-pre-reloc;
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};
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&uart0 {
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u-boot,dm-pre-reloc;
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};
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&uart2 {
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u-boot,dm-pre-reloc;
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};
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&vopb {
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u-boot,dm-pre-reloc;
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};
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&vopl {
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u-boot,dm-pre-reloc;
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};
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