mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 15:26:03 +09:00
b4e85ca0ba
Add support for UHS modes by adding the regulators to power cycle and voltage switch the card. Also add pinmuxes required for each node Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
280 lines
7.5 KiB
Plaintext
280 lines
7.5 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
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*/
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/dts-v1/;
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#include "k3-j7200-som-p0.dtsi"
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#include "k3-j7200-ddr-evm-lp4-1600.dtsi"
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#include "k3-j721e-ddr.dtsi"
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/ {
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aliases {
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remoteproc0 = &sysctrler;
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remoteproc1 = &a72_0;
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};
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chosen {
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stdout-path = &main_uart0;
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tick-timer = &timer1;
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firmware-loader = &fs_loader0;
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};
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fs_loader0: fs_loader@0 {
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u-boot,dm-pre-reloc;
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compatible = "u-boot,fs-loader";
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};
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a72_0: a72@0 {
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compatible = "ti,am654-rproc";
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reg = <0x0 0x00a90000 0x0 0x10>;
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power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
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<&k3_pds 202 TI_SCI_PD_EXCLUSIVE>;
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resets = <&k3_reset 202 0>;
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clocks = <&k3_clks 61 1>;
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assigned-clocks = <&k3_clks 202 2>, <&k3_clks 61 1>;
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assigned-clock-rates = <2000000000>, <200000000>;
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ti,sci = <&dmsc>;
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ti,sci-proc-id = <32>;
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ti,sci-host-id = <10>;
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u-boot,dm-spl;
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};
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clk_200mhz: dummy_clock_200mhz {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <200000000>;
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u-boot,dm-spl;
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};
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clk_19_2mhz: dummy_clock_19_2mhz {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <19200000>;
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u-boot,dm-spl;
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};
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};
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&memorycontroller {
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power-domains = <&k3_pds 8 TI_SCI_PD_SHARED>,
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<&k3_pds 90 TI_SCI_PD_SHARED>;
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clocks = <&k3_clks 8 5>, <&k3_clks 30 9>;
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};
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&cbass_mcu_wakeup {
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mcu_secproxy: secproxy@2a380000 {
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u-boot,dm-spl;
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compatible = "ti,am654-secure-proxy";
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reg = <0x0 0x2a380000 0x0 0x80000>,
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<0x0 0x2a400000 0x0 0x80000>,
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<0x0 0x2a480000 0x0 0x80000>;
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reg-names = "rt", "scfg", "target_data";
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#mbox-cells = <1>;
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};
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sysctrler: sysctrler {
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u-boot,dm-spl;
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compatible = "ti,am654-system-controller";
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mboxes= <&mcu_secproxy 4>, <&mcu_secproxy 5>;
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mbox-names = "tx", "rx";
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};
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};
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&dmsc {
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mboxes= <&mcu_secproxy 8>, <&mcu_secproxy 6>, <&mcu_secproxy 5>;
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mbox-names = "tx", "rx", "notify";
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ti,host-id = <4>;
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ti,secure-host;
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};
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&wkup_pmx0 {
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u-boot,dm-spl;
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wkup_uart0_pins_default: wkup_uart0_pins_default {
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u-boot,dm-spl;
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pinctrl-single,pins = <
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J721E_WKUP_IOPAD(0xb0, PIN_INPUT, 0) /* (B14) WKUP_UART0_RXD */
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J721E_WKUP_IOPAD(0xb4, PIN_OUTPUT, 0) /* (A14) WKUP_UART0_TXD */
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>;
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};
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mcu_uart0_pins_default: mcu_uart0_pins_default {
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u-boot,dm-spl;
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pinctrl-single,pins = <
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J721E_WKUP_IOPAD(0xf4, PIN_INPUT, 0) /* (D20) WKUP_GPIO0_13.MCU_UART0_RXD */
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J721E_WKUP_IOPAD(0xf0, PIN_OUTPUT, 0) /* (D19) WKUP_GPIO0_12.MCU_UART0_TXD */
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J721E_WKUP_IOPAD(0xf8, PIN_INPUT, 0) /* (E20) WKUP_GPIO0_14.MCU_UART0_CTSn */
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J721E_WKUP_IOPAD(0xfc, PIN_OUTPUT, 0) /* (E21) WKUP_GPIO0_15.MCU_UART0_RTSn */
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>;
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};
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wkup_i2c0_pins_default: wkup-i2c0-pins-default {
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pinctrl-single,pins = <
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J721E_WKUP_IOPAD(0x100, PIN_INPUT_PULLUP, 0) /* (F20) WKUP_I2C0_SCL */
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J721E_WKUP_IOPAD(0x104, PIN_INPUT_PULLUP, 0) /* (H21) WKUP_I2C0_SDA */
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>;
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};
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mcu_fss0_hpb0_pins_default: mcu-fss0-hpb0-pins-default {
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pinctrl-single,pins = <
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J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 1) /* (E20) MCU_OSPI0_CLK.MCU_HYPERBUS0_CK */
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J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 1) /* (C21) MCU_OSPI0_LBCLKO.MCU_HYPERBUS0_CKn */
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J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 1) /* (F19) MCU_OSPI0_CSn0.MCU_HYPERBUS0_CSn0 */
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J721E_WKUP_IOPAD(0x54, PIN_OUTPUT, 3) /* (E22) MCU_OSPI1_CSn1.MCU_HYPERBUS0_CSn1 */
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J721E_WKUP_IOPAD(0x30, PIN_OUTPUT, 1) /* (E19) MCU_OSPI0_CSn1.MCU_HYPERBUS0_RESETn */
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J721E_WKUP_IOPAD(0x8, PIN_INPUT, 1) /* (D21) MCU_OSPI0_DQS.MCU_HYPERBUS0_RWDS */
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J721E_WKUP_IOPAD(0xc, PIN_INPUT, 1) /* (D20) MCU_OSPI0_D0.MCU_HYPERBUS0_DQ0 */
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J721E_WKUP_IOPAD(0x10, PIN_INPUT, 1) /* (G19) MCU_OSPI0_D1.MCU_HYPERBUS0_DQ1 */
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J721E_WKUP_IOPAD(0x14, PIN_INPUT, 1) /* (G20) MCU_OSPI0_D2.MCU_HYPERBUS0_DQ2 */
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J721E_WKUP_IOPAD(0x18, PIN_INPUT, 1) /* (F20) MCU_OSPI0_D3.MCU_HYPERBUS0_DQ3 */
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J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 1) /* (F21) MCU_OSPI0_D4.MCU_HYPERBUS0_DQ4 */
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J721E_WKUP_IOPAD(0x20, PIN_INPUT, 1) /* (E21) MCU_OSPI0_D5.MCU_HYPERBUS0_DQ5 */
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J721E_WKUP_IOPAD(0x24, PIN_INPUT, 1) /* (B22) MCU_OSPI0_D6.MCU_HYPERBUS0_DQ6 */
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J721E_WKUP_IOPAD(0x28, PIN_INPUT, 1) /* (G21) MCU_OSPI0_D7.MCU_HYPERBUS0_DQ7 */
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>;
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};
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wkup_gpio_pins_default: wkup-gpio-pins-default {
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pinctrl-single,pins = <
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J721E_WKUP_IOPAD(0xd8, PIN_INPUT, 7) /* (C14) WKUP_GPIO0_6 */
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>;
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};
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};
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&main_pmx0 {
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u-boot,dm-spl;
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main_uart0_pins_default: main_uart0_pins_default {
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u-boot,dm-spl;
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pinctrl-single,pins = <
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J721E_IOPAD(0xb0, PIN_INPUT, 0) /* (T16) UART0_RXD */
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J721E_IOPAD(0xb4, PIN_OUTPUT, 0) /* (T17) UART0_TXD */
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J721E_IOPAD(0xc0, PIN_INPUT, 2) /* (W3) SPI0_CS0.UART0_CTSn */
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J721E_IOPAD(0xc4, PIN_OUTPUT, 2) /* (U5) SPI0_CS1.UART0_RTSn */
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>;
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};
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main_i2c0_pins_default: main-i2c0-pins-default {
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u-boot,dm-spl;
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pinctrl-single,pins = <
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J721E_IOPAD(0xd4, PIN_INPUT_PULLUP, 0) /* (V3) I2C0_SCL */
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J721E_IOPAD(0xd8, PIN_INPUT_PULLUP, 0) /* (W2) I2C0_SDA */
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>;
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};
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main_mmc1_pins_default: main_mmc1_pins_default {
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pinctrl-single,pins = <
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J721E_IOPAD(0x104, PIN_INPUT, 0) /* (M20) MMC1_CMD */
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J721E_IOPAD(0x100, PIN_INPUT, 0) /* (P21) MMC1_CLK */
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J721E_IOPAD(0xfc, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */
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J721E_IOPAD(0xf8, PIN_INPUT, 0) /* (M19) MMC1_DAT0 */
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J721E_IOPAD(0xf4, PIN_INPUT, 0) /* (N21) MMC1_DAT1 */
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J721E_IOPAD(0xf0, PIN_INPUT, 0) /* (N20) MMC1_DAT2 */
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J721E_IOPAD(0xec, PIN_INPUT, 0) /* (N19) MMC1_DAT3 */
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J721E_IOPAD(0xe4, PIN_INPUT, 8) /* (V1) TIMER_IO0.MMC1_SDCD */
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>;
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};
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main_usbss0_pins_default: main_usbss0_pins_default {
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pinctrl-single,pins = <
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J721E_IOPAD(0x120, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS */
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>;
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};
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};
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&wkup_uart0 {
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u-boot,dm-spl;
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pinctrl-names = "default";
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pinctrl-0 = <&wkup_uart0_pins_default>;
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status = "okay";
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};
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&mcu_uart0 {
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/delete-property/ power-domains;
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/delete-property/ clocks;
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/delete-property/ clock-names;
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pinctrl-names = "default";
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pinctrl-0 = <&mcu_uart0_pins_default>;
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status = "okay";
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clock-frequency = <96000000>;
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};
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&main_uart0 {
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status = "okay";
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power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
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pinctrl-names = "default";
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pinctrl-0 = <&main_uart0_pins_default>;
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status = "okay";
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};
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&main_sdhci0 {
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/delete-property/ power-domains;
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/delete-property/ assigned-clocks;
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/delete-property/ assigned-clock-parents;
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pinctrl-0 = <&main_mmc1_pins_default>;
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pinctrl-names = "default";
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clock-names = "clk_xin";
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clocks = <&clk_200mhz>;
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ti,driver-strength-ohm = <50>;
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non-removable;
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bus-width = <8>;
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};
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&main_sdhci1 {
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/delete-property/ power-domains;
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/delete-property/ assigned-clocks;
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/delete-property/ assigned-clock-parents;
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clock-names = "clk_xin";
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clocks = <&clk_200mhz>;
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ti,driver-strength-ohm = <50>;
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};
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&main_i2c0 {
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pinctrl-names = "default";
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pinctrl-0 = <&main_i2c0_pins_default>;
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clock-frequency = <400000>;
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exp1: gpio@20 {
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compatible = "ti,tca6416";
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reg = <0x20>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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exp2: gpio@22 {
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compatible = "ti,tca6424";
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reg = <0x22>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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};
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&usbss0 {
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pinctrl-names = "default";
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pinctrl-0 = <&main_usbss0_pins_default>;
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ti,vbus-divider;
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ti,usb2-only;
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};
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&usb0 {
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dr_mode = "otg";
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maximum-speed = "high-speed";
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};
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&hbmc {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&mcu_fss0_hpb0_pins_default>;
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reg = <0x0 0x47040000 0x0 0x100>,
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<0x0 0x50000000 0x0 0x8000000>;
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ranges = <0x0 0x0 0x0 0x50000000 0x4000000>, /* 64MB Flash on CS0 */
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<0x1 0x0 0x0 0x54000000 0x800000>; /* 8MB flash on CS1 */
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flash@0,0 {
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compatible = "cypress,hyperflash", "cfi-flash";
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reg = <0x0 0x0 0x4000000>;
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};
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};
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#include "k3-j7200-common-proc-board-u-boot.dtsi"
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