mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
34f27b2e86
Added the following registers to the DDR configuration: - ACIOCR0, - ACIOCR3, - V2H_CTL_REG, - DX8SLxDQSCTL. Modified enable_dqs_pd and disable_dqs_pd to only touch the associated bit fields for pullup and pulldown registers (to preserve slew rate and other bits in that same register). Also update the dts files in the same patch to maintain git bisectability. Signed-off-by: James Doublesin <doublesin@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
206 lines
3.4 KiB
Plaintext
206 lines
3.4 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
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*/
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/ {
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memorycontroller: memorycontroller@0298e000 {
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compatible = "ti,am654-ddrss";
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reg = <0x0 0x0298e000 0x0 0x200>,
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<0x0 0x02980000 0x0 0x4000>,
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<0x0 0x02988000 0x0 0x2000>;
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reg-names = "ss", "ctl", "phy";
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clocks = <&k3_clks 20 0>;
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power-domains = <&k3_pds 20 TI_SCI_PD_SHARED>,
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<&k3_pds 244 TI_SCI_PD_SHARED>;
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assigned-clocks = <&k3_clks 20 1>;
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assigned-clock-rates = <DDR_PLL_FREQUENCY>;
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u-boot,dm-spl;
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ti,ss-reg = <
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DDRSS_V2H_CTL_REG
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>;
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ti,ctl-reg = <
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DDRCTL_DFIMISC
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DDRCTL_DFITMG0
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DDRCTL_DFITMG1
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DDRCTL_DFITMG2
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DDRCTL_INIT0
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DDRCTL_INIT1
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DDRCTL_INIT3
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DDRCTL_INIT4
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DDRCTL_INIT5
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DDRCTL_INIT6
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DDRCTL_INIT7
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DDRCTL_MSTR
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DDRCTL_ODTCFG
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DDRCTL_ODTMAP
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DDRCTL_RANKCTL
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DDRCTL_RFSHCTL0
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DDRCTL_RFSHTMG
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DDRCTL_ZQCTL0
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DDRCTL_ZQCTL1
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>;
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ti,ctl-crc = <
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DDRCTL_CRCPARCTL0
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DDRCTL_CRCPARCTL1
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DDRCTL_CRCPARCTL2
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>;
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ti,ctl-ecc = <
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DDRCTL_ECCCFG0
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>;
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ti,ctl-map = <
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DDRCTL_ADDRMAP0
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DDRCTL_ADDRMAP1
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DDRCTL_ADDRMAP2
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DDRCTL_ADDRMAP3
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DDRCTL_ADDRMAP4
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DDRCTL_ADDRMAP5
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DDRCTL_ADDRMAP6
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DDRCTL_ADDRMAP7
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DDRCTL_ADDRMAP8
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DDRCTL_ADDRMAP9
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DDRCTL_ADDRMAP10
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DDRCTL_ADDRMAP11
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DDRCTL_DQMAP0
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DDRCTL_DQMAP1
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DDRCTL_DQMAP4
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DDRCTL_DQMAP5
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>;
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ti,ctl-pwr = <
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DDRCTL_PWRCTL
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>;
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ti,ctl-timing = <
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DDRCTL_DRAMTMG0
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DDRCTL_DRAMTMG1
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DDRCTL_DRAMTMG2
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DDRCTL_DRAMTMG3
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DDRCTL_DRAMTMG4
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DDRCTL_DRAMTMG5
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DDRCTL_DRAMTMG6
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DDRCTL_DRAMTMG7
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DDRCTL_DRAMTMG8
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DDRCTL_DRAMTMG9
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DDRCTL_DRAMTMG11
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DDRCTL_DRAMTMG12
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DDRCTL_DRAMTMG13
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DDRCTL_DRAMTMG14
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DDRCTL_DRAMTMG15
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DDRCTL_DRAMTMG17
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>;
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ti,phy-cfg = <
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DDRPHY_DCR
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DDRPHY_DSGCR
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DDRPHY_DX0GCR0
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DDRPHY_DX0GCR1
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DDRPHY_DX0GCR2
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DDRPHY_DX0GCR3
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DDRPHY_DX0GCR4
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DDRPHY_DX0GCR5
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DDRPHY_DX0GTR0
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DDRPHY_DX1GCR0
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DDRPHY_DX1GCR1
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DDRPHY_DX1GCR2
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DDRPHY_DX1GCR3
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DDRPHY_DX1GCR4
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DDRPHY_DX1GCR5
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DDRPHY_DX1GTR0
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DDRPHY_DX2GCR0
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DDRPHY_DX2GCR1
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DDRPHY_DX2GCR2
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DDRPHY_DX2GCR3
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DDRPHY_DX2GCR4
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DDRPHY_DX2GCR5
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DDRPHY_DX2GTR0
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DDRPHY_DX3GCR0
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DDRPHY_DX3GCR1
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DDRPHY_DX3GCR2
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DDRPHY_DX3GCR3
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DDRPHY_DX3GCR4
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DDRPHY_DX3GCR5
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DDRPHY_DX3GTR0
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DDRPHY_DX4GCR0
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DDRPHY_DX4GCR1
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DDRPHY_DX4GCR2
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DDRPHY_DX4GCR3
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DDRPHY_DX4GCR4
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DDRPHY_DX4GCR5
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DDRPHY_DX4GTR0
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DDRPHY_DX8SL0DXCTL2
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DDRPHY_DX8SL0IOCR
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DDRPHY_DX8SL0PLLCR0
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DDRPHY_DX8SL0DQSCTL
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DDRPHY_DX8SL1DXCTL2
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DDRPHY_DX8SL1IOCR
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DDRPHY_DX8SL1PLLCR0
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DDRPHY_DX8SL1DQSCTL
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DDRPHY_DX8SL2DXCTL2
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DDRPHY_DX8SL2IOCR
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DDRPHY_DX8SL2PLLCR0
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DDRPHY_DX8SL2DQSCTL
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DDRPHY_DXCCR
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DDRPHY_ODTCR
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DDRPHY_PGCR0
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DDRPHY_PGCR1
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DDRPHY_PGCR2
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DDRPHY_PGCR3
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DDRPHY_PGCR5
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DDRPHY_PGCR6
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>;
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ti,phy-ctl = <
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DDRPHY_DTCR0
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DDRPHY_DTCR1
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DDRPHY_MR0
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DDRPHY_MR1
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DDRPHY_MR2
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DDRPHY_MR3
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DDRPHY_MR4
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DDRPHY_MR5
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DDRPHY_MR6
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DDRPHY_MR11
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DDRPHY_MR12
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DDRPHY_MR13
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DDRPHY_MR14
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DDRPHY_MR22
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DDRPHY_PLLCR0
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DDRPHY_VTCR0
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>;
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ti,phy-ioctl = <
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DDRPHY_ACIOCR0
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DDRPHY_ACIOCR3
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DDRPHY_ACIOCR5
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DDRPHY_IOVCR0
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>;
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ti,phy-timing = <
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DDRPHY_DTPR0
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DDRPHY_DTPR1
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DDRPHY_DTPR2
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DDRPHY_DTPR3
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DDRPHY_DTPR4
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DDRPHY_DTPR5
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DDRPHY_DTPR6
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DDRPHY_PTR2
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DDRPHY_PTR3
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DDRPHY_PTR4
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DDRPHY_PTR5
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DDRPHY_PTR6
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>;
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ti,phy-zq = <
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DDRPHY_ZQ0PR0
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DDRPHY_ZQ1PR0
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DDRPHY_ZQCR
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>;
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};
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};
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