mirror of
https://github.com/brain-hackers/u-boot-brain
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7b5b934313
Add support for i.MX8X based Capricorn Giedi SoM. Supported interfaces: GPIO, ENET, eMMC, I2C, UART. Console output: U-Boot SPL 2020.01-00003-gfd1c98f (Jan 07 2020 - 15:51:25 +0100) Trying to boot from MMC1 Load image from MMC/SD 0x3e400 U-Boot 2020.01-00003-gfd1c98f (Jan 07 2020 - 15:51:25 +0100) ##v01.07 CPU: NXP i.MX8QXP RevB A35 at 1200 MHz at 30C Model: Siemens Giedi Board: Capricorn Boot: MMC0 DRAM: 1022 MiB MMC: FSL_SDHC: 0 Loading Environment from MMC... OK In: serial@5a080000 Out: serial@5a080000 Err: serial@5a080000 Net: eth1: ethernet@5b050000 [PRIME] Autobooting in 1 seconds, press "<Esc><Esc>" to stop Signed-off-by: Anatolij Gustschin <agust@denx.de>
286 lines
6.1 KiB
Plaintext
286 lines
6.1 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2017 NXP
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*
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* Copyright 2019 Siemens AG
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*
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*/
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/dts-v1/;
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#include "fsl-imx8qxp.dtsi"
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#include "imx8qxp-capricorn-u-boot.dtsi"
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/ {
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model = "Siemens Giedi";
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compatible = "siemens,capricorn", "fsl,imx8qxp";
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chosen {
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bootargs = "console=ttyLP2,115200 earlycon=lpuart32,0x5a080000,115200";
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stdout-path = &lpuart2;
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};
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leds {
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compatible = "gpio-leds";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gpio_leds>;
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run {
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label = "run";
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gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>;
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default-state = "on";
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};
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flt {
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label = "flt";
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gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>;
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default-state = "on";
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};
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svc {
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label = "svc";
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gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
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default-state = "on";
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};
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com1_tx {
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label = "com1-tx";
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gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>;
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default-state = "on";
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};
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com1_rx {
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label = "com1-rx";
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gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>;
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default-state = "on";
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};
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com2_tx {
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label = "com2-tx";
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gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>;
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default-state = "on";
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};
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com2_rx {
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label = "com2-rx";
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gpios = <&gpio0 29 GPIO_ACTIVE_HIGH>;
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default-state = "on";
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};
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cloud {
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label = "cloud";
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gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
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default-state = "on";
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};
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wlan {
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label = "wlan";
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gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>;
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default-state = "on";
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};
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dbg1 {
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label = "dbg1";
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gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>;
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default-state = "on";
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};
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dbg2 {
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label = "dbg2";
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gpios = <&gpio3 17 GPIO_ACTIVE_HIGH>;
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default-state = "on";
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};
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dbg3 {
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label = "dbg3";
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gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>;
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default-state = "on";
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};
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dbg4 {
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label = "dbg4";
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gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
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default-state = "on";
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};
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};
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};
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&iomuxc {
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pinctrl-names = "default";
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muxcgrp: imx8qxp-som {
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pinctrl_gpio_leds: gpioledsgrp {
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fsl,pins = <
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SC_P_ESAI0_FST_LSIO_GPIO0_IO01 0x06000021
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SC_P_ESAI0_TX0_LSIO_GPIO0_IO04 0x06000021
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SC_P_SAI0_TXC_LSIO_GPIO0_IO26 0x06000021
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SC_P_SAI1_RXD_LSIO_GPIO0_IO29 0x06000021
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SC_P_FLEXCAN1_RX_LSIO_GPIO1_IO17 0x06000021
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SC_P_FLEXCAN1_TX_LSIO_GPIO1_IO18 0x06000021
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SC_P_QSPI0B_SCLK_LSIO_GPIO3_IO17 0x06000021
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SC_P_QSPI0B_DATA0_LSIO_GPIO3_IO18 0x06000021
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SC_P_QSPI0B_DATA1_LSIO_GPIO3_IO19 0x06000021
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SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03 0x06000021
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SC_P_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00 0x06000021
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SC_P_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 0x06000021
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SC_P_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 0x06000021
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>;
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};
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pinctrl_lpi2c0: lpi2c0grp {
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fsl,pins = <
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SC_P_MIPI_CSI0_GPIO0_00_ADMA_I2C0_SCL 0x0C000020
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SC_P_MIPI_CSI0_GPIO0_01_ADMA_I2C0_SDA 0x0C000020
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>;
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};
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pinctrl_lpi2c1: lpi2c1grp {
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fsl,pins = <
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SC_P_MIPI_DSI0_GPIO0_00_ADMA_I2C1_SCL 0x0C000020
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SC_P_MIPI_DSI0_GPIO0_01_ADMA_I2C1_SDA 0x0C000020
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>;
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};
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pinctrl_lpuart2: lpuart2grp {
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fsl,pins = <
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SC_P_UART2_RX_ADMA_UART2_RX 0x06000020
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SC_P_UART2_TX_ADMA_UART2_TX 0x06000020
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>;
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};
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pinctrl_usdhc1: usdhc1grp {
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fsl,pins = <
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SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
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SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
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SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
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SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
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SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021
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SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021
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SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021
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SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021
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SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021
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SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021
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SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000041
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SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021
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SC_P_ENET0_RGMII_TXC_LSIO_GPIO4_IO29 0x06000021
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>;
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};
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pinctrl_usdhc2: usdhc2grp {
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fsl,pins = <
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SC_P_ENET0_RGMII_RXC_CONN_USDHC1_CLK 0x06000041
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SC_P_ENET0_RGMII_RX_CTL_CONN_USDHC1_CMD 0x00000021
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SC_P_ENET0_RGMII_RXD0_CONN_USDHC1_DATA0 0x00000021
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SC_P_ENET0_RGMII_RXD1_CONN_USDHC1_DATA1 0x00000021
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SC_P_ENET0_RGMII_RXD2_CONN_USDHC1_DATA2 0x00000021
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SC_P_ENET0_RGMII_RXD3_CONN_USDHC1_DATA3 0x00000021
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SC_P_ENET0_RGMII_TXD2_CONN_USDHC1_CD_B 0x06000021
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//SC_P_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 0x06000021
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SC_P_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30 0x06000021
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>;
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};
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pinctrl_fec2: fec2grp {
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fsl,pins = <
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SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0
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SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x000014a0
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SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0
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SC_P_ENET0_MDC_CONN_ENET1_MDC 0x00000060
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SC_P_ENET0_MDIO_CONN_ENET1_MDIO 0x00000060
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SC_P_ESAI0_FSR_CONN_ENET1_RCLK50M_IN 0x00000060
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SC_P_SPDIF0_RX_CONN_ENET1_RGMII_RXD0 0x00000060
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SC_P_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1 0x00000060
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SC_P_ESAI0_TX2_RX3_CONN_ENET1_RMII_RX_ER 0x00000060
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SC_P_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL 0x00000060
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SC_P_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0 0x00000060
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SC_P_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1 0x00000060
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SC_P_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL 0x00000060 /* ERST: Reset pin */
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>;
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};
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};
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};
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&i2c0 {
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_lpi2c0>;
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status = "okay";
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};
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&i2c1 {
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_lpi2c1>;
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status = "okay";
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};
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&lpuart2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_lpuart2>;
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status = "okay";
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};
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&usdhc1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc1>;
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clock-frequency=<52000000>;
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no-1-8-v;
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bus-width = <8>;
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non-removable;
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status = "okay";
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};
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&gpio0 {
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status = "okay";
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};
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&gpio1 {
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status = "okay";
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};
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&gpio2 {
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status = "okay";
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};
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&gpio3 {
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status = "okay";
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};
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&gpio4 {
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status = "okay";
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};
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&gpio5 {
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status = "okay";
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};
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&fec1 {
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status ="disabled";
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};
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&fec2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec2>;
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phy-mode = "rmii";
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phy-handle = <ðphy1>;
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fsl,magic-packet;
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy0: ethernet-phy@0 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <0>;
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};
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ethphy1: ethernet-phy@1 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <1>;
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};
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};
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};
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