mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 07:16:04 +09:00
9452d58e10
This patch converts the dart6ul ethernet support to DM_ETH and cleans up the legacy ethernet code. The clean up, more specifically: * moves the fec2 node and pin definition to the carrier board DTS since the phy associated with it is on the carrier board and not on the SoM; * add the reset pin associated to each phy; * separate the ethernet, mdio and reset pins of each fec so that they are easier to reference; * add clock properties to the phy nodes since they are connected to the 50Mhz ENET[12]_TX_CLK clock of the SoC; * remove CONFIG_BOARD_EARLY_INIT_F since the function is now empty. Signed-off-by: Marc Ferland <ferlandm@amotus.ca>
88 lines
1.9 KiB
Plaintext
88 lines
1.9 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+
|
|
/*
|
|
* Copyright (C) 2019 Parthiban Nallathambi <parthitce@gmail.com>
|
|
* Copyright (C) 2021 Marc Ferland, Amotus Solutions Inc., <ferlandm@amotus.ca>
|
|
*/
|
|
|
|
/dts-v1/;
|
|
|
|
#include "imx6ull.dtsi"
|
|
#include "imx6ull-dart-6ul.dtsi"
|
|
|
|
/ {
|
|
model = "Variscite DART-6UL Evaluation Kit";
|
|
compatible = "variscite,imx6ull-dart-6ul", "fsl,imx6ull";
|
|
};
|
|
|
|
&mdio1 {
|
|
/* KSZ8081RNB (carrier-board) */
|
|
ethphy1: ethernet-phy@3 {
|
|
compatible = "ethernet-phy-ieee802.3-c22";
|
|
clocks = <&clks IMX6UL_CLK_ENET2_REF>;
|
|
clock-names = "rmii-ref";
|
|
micrel,led-mode = <1>;
|
|
max-speed = <100>;
|
|
reg = <3>;
|
|
};
|
|
};
|
|
|
|
&fec2 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_enet2 &pinctrl_enet2_rst>;
|
|
phy-mode = "rmii";
|
|
phy-handle = <ðphy1>;
|
|
phy-reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
|
|
phy-reset-duration = <100>;
|
|
status = "okay";
|
|
};
|
|
|
|
&usdhc2 {
|
|
status = "okay";
|
|
};
|
|
|
|
&usbotg1 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_usb_otg1_id>;
|
|
dr_mode = "otg";
|
|
srp-disable;
|
|
hnp-disable;
|
|
adp-disable;
|
|
status = "okay";
|
|
};
|
|
|
|
&iomuxc {
|
|
pinctrl-names = "default";
|
|
|
|
pinctrl_usb_otg1_id: usbotg1idgrp {
|
|
fsl,pins = <
|
|
MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059
|
|
>;
|
|
};
|
|
|
|
pinctrl_enet2: enet2grp {
|
|
fsl,pins = <
|
|
MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
|
|
MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
|
|
MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
|
|
MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
|
|
MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
|
|
MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
|
|
MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
|
|
MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031
|
|
>;
|
|
};
|
|
|
|
pinctrl_enet2_mdio: mdio_enet2_grp {
|
|
fsl,pins = <
|
|
MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
|
|
MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
|
|
>;
|
|
};
|
|
|
|
pinctrl_enet2_rst: enet2-rst-grp {
|
|
fsl,pins = <
|
|
MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x1b0b0
|
|
>;
|
|
};
|
|
};
|