mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
f8f9f79a63
Migrate to using device tree required for further driver model integration. Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
70 lines
1.8 KiB
Plaintext
70 lines
1.8 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+
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//
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// Copyright 2013-2019 Boundary Devices, Inc.
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// Copyright 2012 Freescale Semiconductor, Inc.
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// Copyright 2011 Linaro Ltd.
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#include "imx6qdl-sabrelite.dtsi"
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&iomuxc {
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pinctrl_enet: enetgrp {
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fsl,pins = <
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MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
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MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
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MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x100b0
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MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x100b0
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MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x100b0
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MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x100b0
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MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x100b0
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MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0
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MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0
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MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
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MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
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MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
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MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
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MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
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MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
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#undef GP_ENET_PHY_RESET
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#define GP_ENET_PHY_RESET <&gpio1 27 GPIO_ACTIVE_LOW>
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MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x030b0
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#define GPIRQ_ENET_PHY <&gpio1 28 IRQ_TYPE_LEVEL_LOW>
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MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0
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>;
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};
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pinctrl_hog: hoggrp {
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fsl,pins = <
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/* Spare */
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MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1b0b0
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MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x1b0b0
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MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0
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>;
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};
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pinctrl_uart3: uart3grp {
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fsl,pins = <
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MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
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MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
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MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1
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MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1
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>;
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};
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};
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&fec {
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#if 0
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phy-reset-gpios = GP_ENET_PHY_RESET;
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#endif
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};
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&uart3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart3>;
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uart-has-rtscts;
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status = "okay";
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};
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&usdhc3 {
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/delete-property/ wp-gpios;
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};
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