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https://github.com/brain-hackers/u-boot-brain
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b62526282a
Add support for selecting the appropriate DTS file depending on the SERDES protocol used. The fsl-ls2088a-qds DTS will be used by default if there isn't a DTS file specifically made for the current SERDES protocol. This patch adds support for the on-board ports (DPMAC 1,2 and 4,5) found on the SERDES protocols 21(0x15) and 29(0x1d) for SD#1. On the LS1088AQDS board EMDIO1 is used with two onboard RGMII PHYs (Realtek RTL8211FD-CG), as well as 2 input/output connectors for mezzanine cards. Configuration signals from the Qixis FPGA control the routing of the external MDIOs. Register 0x54 of the Qixis FPGA controls the routing of the EMDIO1 one of the 2 IO slots. As a consequence, a new node is added to describe register 0x54 as a MDIO mux controlled with child nodes describing all the IO slots as MDIO buses. Also, in case CONFIG_DM_ETH and CONFIG_MULTI_DTB_FIT are enabled implement the board_fit_config_name_match() function in order to choose the appropriate DTS. Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
31 lines
503 B
Plaintext
31 lines
503 B
Plaintext
// SPDX-License-Identifier: GPL-2.0+ OR X11
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/*
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* NXP LS1088AQDS device tree source for SERDES block #1 - protocol 21 (0x15)
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*
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* Copyright 2020 NXP
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*/
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#include "fsl-ls1088a-qds.dtsi"
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&dpmac1 {
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status = "okay";
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phy-connection-type = "xfi";
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};
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&dpmac2 {
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status = "okay";
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phy-connection-type = "xfi";
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};
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&dpmac4 {
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status = "okay";
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phy-handle = <&rgmii_phy1>;
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phy-connection-type = "rgmii-id";
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};
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&dpmac5 {
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status = "okay";
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phy-handle = <&rgmii_phy2>;
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phy-connection-type = "rgmii-id";
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};
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