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https://github.com/brain-hackers/u-boot-brain
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a7fdac7e2a
Includes DT definition for the following serdes protocols using various PHY cards: 85xx, 13xx, 65xx, 9999, 7777. Note that the default device tree for QDS now uses 85xx. Enabling any of the others requires patching the fsl-ls1028a-qds.dtsi file (the includes at the bottom of the file). The phy-handle is specified as a path rather than a label because it is possible to use the #include multiple times (meaning that more than one PHY riser card of one type is inserted), and therefore, there would be duplicate labels with the same name. LBRW means that the board needs lane B rework before using this dtsi. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
264 lines
3.6 KiB
Plaintext
264 lines
3.6 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+ OR X11
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/*
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* NXP ls1028AQDS device tree source
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*
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* Copyright 2019 NXP
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*
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*/
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/dts-v1/;
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#include "fsl-ls1028a.dtsi"
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/ {
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model = "NXP Layerscape 1028a QDS Board";
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compatible = "fsl,ls1028a-qds", "fsl,ls1028a";
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aliases {
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spi0 = &fspi;
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spi1 = &dspi0;
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spi2 = &dspi1;
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spi3 = &dspi2;
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};
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};
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&dspi0 {
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bus-num = <0>;
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status = "okay";
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dflash0: sst25wf040b {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "spi-flash";
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spi-max-frequency = <3000000>;
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spi-cpol;
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spi-cpha;
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reg = <0>;
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};
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dflash1: en25s64 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "spi-flash";
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spi-max-frequency = <3000000>;
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spi-cpol;
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spi-cpha;
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reg = <1>;
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};
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dflash2: n25q128a {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "spi-flash";
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spi-max-frequency = <3000000>;
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spi-cpol;
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spi-cpha;
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reg = <2>;
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};
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};
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&dspi1 {
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bus-num = <0>;
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status = "okay";
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dflash3: sst25wf040b {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "spi-flash";
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spi-max-frequency = <3000000>;
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spi-cpol;
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spi-cpha;
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reg = <0>;
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};
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dflash4: en25s64 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "spi-flash";
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spi-max-frequency = <3000000>;
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spi-cpol;
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spi-cpha;
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reg = <1>;
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};
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dflash5: n25q128a {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "spi-flash";
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spi-max-frequency = <3000000>;
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spi-cpol;
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spi-cpha;
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reg = <2>;
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};
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};
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&dspi2 {
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bus-num = <0>;
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status = "okay";
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dflash8: en25s64 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "spi-flash";
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spi-max-frequency = <3000000>;
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spi-cpol;
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spi-cpha;
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reg = <0>;
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};
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};
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&esdhc0 {
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status = "okay";
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};
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&esdhc1 {
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status = "okay";
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};
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&fspi {
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status = "okay";
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mt35xu02g0: flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "jedec,spi-nor";
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spi-max-frequency = <50000000>;
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reg = <0>;
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spi-rx-bus-width = <8>;
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spi-tx-bus-width = <1>;
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};
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};
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&i2c0 {
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status = "okay";
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u-boot,dm-pre-reloc;
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fpga@66 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "simple-mfd";
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reg = <0x66>;
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mux-mdio@54 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "mdio-mux-i2creg";
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reg = <0x54>;
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#mux-control-cells = <1>;
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mux-reg-masks = <0x54 0xf0>;
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mdio-parent-bus = <&mdio0>;
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/* on-board MDIO with a single RGMII PHY */
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mdio@00 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x00>;
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qds_phy0: phy@5 {
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reg = <5>;
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};
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};
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/* slot 1 */
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slot1: mdio@40 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40>;
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};
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/* slot 2 */
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slot2: mdio@50 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x50>;
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};
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/* slot 3 */
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slot3: mdio@60 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x60>;
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};
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/* slot 4 */
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slot4: mdio@70 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x70>;
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};
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};
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};
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i2c-mux@77 {
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compatible = "nxp,pca9547";
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reg = <0x77>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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&i2c1 {
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status = "okay";
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rtc@51 {
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compatible = "pcf2127-rtc";
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reg = <0x51>;
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};
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};
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&i2c2 {
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status = "okay";
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};
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&i2c3 {
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status = "okay";
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};
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&i2c4 {
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status = "okay";
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};
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&i2c5 {
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status = "okay";
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};
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&i2c6 {
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status = "okay";
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};
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&i2c7 {
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status = "okay";
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};
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&lpuart0 {
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status = "okay";
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};
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&sata {
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status = "okay";
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};
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&serial0 {
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status = "okay";
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};
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&serial1 {
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status = "okay";
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};
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&usb1 {
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status = "okay";
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};
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&usb2 {
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status = "okay";
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};
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&enetc1 {
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status = "okay";
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phy-mode = "rgmii";
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phy-handle = <&qds_phy0>;
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};
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&mdio0 {
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status = "okay";
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};
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#include "fsl-ls1028a-qds-8xxx-sch-24801.dtsi"
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#include "fsl-ls1028a-qds-x5xx-sch-28021-LBRW.dtsi"
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