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https://github.com/brain-hackers/u-boot-brain
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2bf4658b8c
It was noticed that the clock isn't continuously enabled when there is no link. This is because the 125MHz clock is derived from the internal PLL which seems to go into some kind of power-down mode every once in a while. The LS1028A expects a contiuous clock. Thus enable the PLL all the time. Also, the RGMII pad voltage is wrong, it was configured to 2.5V (that is the VDDH regulator). The correct voltage is 1.8V, i.e. the VDDIO regulator. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
59 lines
1.3 KiB
Plaintext
59 lines
1.3 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Device Tree file for the Kontron SMARC-sAL28 board.
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*
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* This is for the network variant 1 which has one ethernet port. It is
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* different than the base variant, which also has one port, but here the
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* port is connected via RGMII. This port is not TSN aware.
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* None of the four SerDes lanes are used by the module, instead they are
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* all led out to the carrier for customer use.
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*
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* Copyright (C) 2020 Michael Walle <michael@walle.cc>
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*
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*/
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/dts-v1/;
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#include "fsl-ls1028a-kontron-sl28.dts"
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#include <dt-bindings/net/qca-ar803x.h>
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/ {
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model = "Kontron SMARC-sAL28 (4 Lanes)";
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compatible = "kontron,sl28-var1", "kontron,sl28", "fsl,ls1028a";
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};
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&enetc0 {
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status = "disabled";
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/delete-property/ phy-handle;
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};
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&enetc1 {
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phy-handle = <&phy0>;
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phy-mode = "rgmii-id";
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status = "okay";
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};
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/delete-node/ &phy0;
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&mdio0 {
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phy0: ethernet-phy@4 {
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reg = <0x4>;
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eee-broken-1000t;
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eee-broken-100tx;
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qca,clk-out-frequency = <125000000>;
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qca,clk-out-strength = <AR803X_STRENGTH_FULL>;
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qca,keep-pll-enabled;
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vddio-supply = <&vddio>;
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vddio: vddio-regulator {
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regulator-name = "VDDIO";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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};
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vddh: vddh-regulator {
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regulator-name = "VDDH";
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};
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};
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};
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