74 lines
1.9 KiB
Plaintext
74 lines
1.9 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2018 Marvell International Ltd.
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*/
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/*
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* Device Tree file for the CN 9030 SoC, made of an AP806 Quad and
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* one CP110.
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*/
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#include <dt-bindings/gpio/gpio.h>
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#include "armada-common.dtsi"
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#include "armada-ap807.dtsi"
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#include "armada-ap80x-quad.dtsi"
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/* This defines used to calculate the base address of each CP */
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#define CP110_BASE_OFFSET (0xf2000000)
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#define CP110_SPACE_SIZE (0x02000000)
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#define CP110_BASE (CP110_BASE_OFFSET + \
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(CP110_NUM * CP110_SPACE_SIZE))
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#define CP110_PCIE_MEM_SIZE(iface) ((iface == 0) ? 0x1ff00000 : 0xf00000)
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#define CP110_PCIE_BUS_MEM_CFG (0x82000000)
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/* CP110-0 Settings */
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#define CP110_NAME cp0
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#define CP110_NUM 0
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#define CP110_PCIEx_CPU_MEM_BASE(iface) ((iface == 0) ? 0xc0000000 : \
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(0xe0000000 + (iface - 1) * 0x1000000))
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#define CP110_PCIEx_BUS_MEM_BASE(iface) (CP110_PCIEx_CPU_MEM_BASE(iface))
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#include "armada-cp110.dtsi"
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/ {
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model = "Marvell CN 9030";
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compatible = "marvell,armada70x0", "marvell,armada-ap806-quad",
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"marvell,armada-ap806";
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};
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&cp0_pinctl {
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compatible = "marvell,mvebu-pinctrl", "marvell,armada-8k-cpm-pinctrl";
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bank-name ="cp0-110";
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cp0_i2c0_pins: cp0-i2c-pins-0 {
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marvell,pins = < 37 38 >;
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marvell,function = <2>;
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};
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cp0_i2c1_pins: cp0-i2c-pins-1 {
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marvell,pins = < 35 36 >;
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marvell,function = <2>;
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};
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cp0_ge1_rgmii_pins: cp0-ge-rgmii-pins-0 {
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marvell,pins = < 0 1 2 3 4 5 6 7 8 9 10 11>;
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marvell,function = <3>;
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};
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cp0_ge2_rgmii_pins: cp0-ge-rgmii-pins-1 {
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marvell,pins = < 44 45 46 47 48 49 50 51
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52 53 54 55 >;
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marvell,function = <1>;
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};
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cp0_pca0_pins: cp0-pca0_pins {
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marvell,pins = <62>;
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marvell,function = <0>;
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};
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cp0_sdhci_pins: cp0-sdhi-pins-0 {
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marvell,pins = < 56 57 58 59 60 61 >;
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marvell,function = <14>;
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};
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cp0_spi0_pins: cp0-spi-pins-0 {
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marvell,pins = < 13 14 15 16 >;
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marvell,function = <3>;
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};
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};
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