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https://github.com/brain-hackers/u-boot-brain
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2dbba24088
Currently, all comphy definitions are PHY_TYPE_XX and PHY_SPEEED_XX. Those definition might be confused with MDIO PHY definitions. This patch does the following changes: - PHY_TYPE_XX --> COMPHY_TYPE_XX - PHY_SPEED_XX --> COMPHY_SPEED_XX This improves readability, no functional change. Change-Id: I2bd1d9289ebbc5c16fa80f9870f797ea1bcaf5fa Signed-off-by: Igal Liberman <igall@marvell.com> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
187 lines
3.1 KiB
Plaintext
187 lines
3.1 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2016- 2021 Marvell International Ltd.
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*/
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/*
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* Device Tree file for Marvell Armada 7040 Development board platform
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* Boot device: NAND, 0xE (SW3)
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*/
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#include "armada-7040.dtsi"
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/ {
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model = "Marvell Armada 7040 DB board with NAND";
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compatible = "marvell,armada7040-db-nand", "marvell,armada7040-db",
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"marvell,armada7040", "marvell,armada-ap806-quad",
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"marvell,armada-ap806";
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chosen {
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stdout-path = "serial0:115200n8";
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};
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aliases {
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i2c0 = &cp0_i2c0;
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spi0 = &cp0_spi1;
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};
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memory@00000000 {
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device_type = "memory";
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reg = <0x0 0x0 0x0 0x80000000>;
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};
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};
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&ap_pinctl {
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/* MPP Bus:
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* SDIO [0-5]
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* UART0 [11,19]
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*/
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/* 0 1 2 3 4 5 6 7 8 9 */
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pin-func = < 0x1 0x1 0x1 0x1 0x1 0x1 0x0 0x0 0x0 0x0
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0x0 0x3 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x3 >;
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};
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&uart0 {
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status = "okay";
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};
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&cp0_pcie2 {
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status = "okay";
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};
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&cp0_i2c0 {
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pinctrl-names = "default";
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pinctrl-0 = <&cp0_i2c0_pins>;
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status = "okay";
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clock-frequency = <100000>;
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};
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&cp0_pinctl {
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/* MPP Bus:
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* AUDIO [0-5]
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* GBE [6-11]
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* SS_PWDN [12]
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* NF_RBn [13]
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* GPIO [14]
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* DEV_BUS [15-27]
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* SATA1 [28]
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* UART0 [29-30]
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* MSS_VTT_EN [31]
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* SMI [32,34]
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* XSMI [35-36]
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* I2C [37-38]
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* RGMII1 [44-55]
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* SD [56-61]
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* GPIO [62]
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*/
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/* 0 1 2 3 4 5 6 7 8 9 */
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pin-func = < 0x2 0x2 0x2 0x2 0x2 0x2 0x3 0x3 0x3 0x3
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0x3 0x3 0x0 0x2 0x0 0x1 0x1 0x1 0x1 0x1
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0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x9 0xa
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0xa 0x0 0x7 0x0 0x7 0x7 0x7 0x2 0x2 0x0
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0x0 0x0 0x0 0x0 0x1 0x1 0x1 0x1 0x1 0x1
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0x1 0x1 0x1 0x1 0x1 0x1 0xe 0xe 0xe 0xe
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0xe 0xe 0x0>;
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};
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&cp0_spi1 {
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pinctrl-names = "default";
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pinctrl-0 = <&cp0_spi0_pins>;
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status = "disabled";
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spi-flash@0 {
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#address-cells = <0x1>;
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#size-cells = <0x1>;
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compatible = "jedec,spi-nor";
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reg = <0x0>;
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spi-max-frequency = <20000000>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "U-Boot";
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reg = <0x0 0x200000>;
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};
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partition@400000 {
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label = "Filesystem";
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reg = <0x200000 0xe00000>;
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};
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};
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};
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};
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&cp0_sata0 {
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status = "okay";
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};
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&cp0_usb3_0 {
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status = "okay";
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};
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&cp0_usb3_1 {
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status = "okay";
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};
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&cp0_comphy {
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phy0 {
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phy-type = <COMPHY_TYPE_SGMII2>;
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phy-speed = <COMPHY_SPEED_3_125G>;
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};
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phy1 {
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phy-type = <COMPHY_TYPE_USB3_HOST0>;
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phy-speed = <COMPHY_SPEED_5G>;
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};
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phy2 {
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phy-type = <COMPHY_TYPE_SGMII0>;
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phy-speed = <COMPHY_SPEED_1_25G>;
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};
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phy3 {
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phy-type = <COMPHY_TYPE_SATA1>;
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phy-speed = <COMPHY_SPEED_5G>;
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};
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phy4 {
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phy-type = <COMPHY_TYPE_USB3_HOST1>;
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phy-speed = <COMPHY_SPEED_5G>;
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};
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phy5 {
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phy-type = <COMPHY_TYPE_PEX2>;
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phy-speed = <COMPHY_SPEED_5G>;
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};
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};
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&cp0_nand {
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status = "okay";
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};
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&cp0_utmi0 {
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status = "okay";
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};
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&cp0_utmi1 {
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status = "okay";
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};
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&ap_sdhci0 {
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status = "okay";
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bus-width = <4>;
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no-1-8-v;
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non-removable;
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};
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&cp0_sdhci0 {
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status = "okay";
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bus-width = <4>;
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no-1-8-v;
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non-removable;
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};
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