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https://github.com/brain-hackers/u-boot-brain
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079b35a261
For some configurations with more PCIe cards and PCIe bridges, 16 MiB of PCIe MEM space may not be enough. Since TF-A already allocates a 128 MiB CPU window for PCIe, and since IO port space is only 64 KiB in total, use all the remaining space (64 + 32 + 16 + 8 + 4 + 2 + 1 = 127 MiB) for PCIe MEM. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
349 lines
8.9 KiB
Plaintext
349 lines
8.9 KiB
Plaintext
/*
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* Device Tree Include file for Marvell Armada 37xx family of SoCs.
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*
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* Copyright (C) 2016 Marvell
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*
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* Gregory CLEMENT <gregory.clement@free-electrons.com>
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This file is distributed in the hope that it will be useful
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/comphy/comphy_data.h>
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#include <dt-bindings/gpio/gpio.h>
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/ {
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model = "Marvell Armada 37xx SoC";
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compatible = "marvell,armada3700";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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aliases {
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serial0 = &uart0;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0>;
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enable-method = "psci";
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};
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};
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13
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(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 14
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(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 11
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(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 10
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(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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internal-regs {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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/* 32M internal register @ 0xd000_0000 */
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ranges = <0x0 0x0 0xd0000000 0x2000000>;
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uart0: serial@12000 {
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compatible = "marvell,armada-3700-uart";
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reg = <0x12000 0x400>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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wdt: watchdog-timer@8300 {
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compatible = "marvell,armada-3700-wdt";
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reg = <0xd064 0x4>,
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<0x8300 0x40>;
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};
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nb_periph_clk: nb-periph-clk@13000 {
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compatible = "marvell,armada-3700-periph-clock-nb";
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reg = <0x13000 0x100>;
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clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>, <&tbg 3>;
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#clock-cells = <1>;
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};
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sb_periph_clk: sb-periph-clk@18000 {
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compatible = "marvell,armada-3700-periph-clock-sb";
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reg = <0x18000 0x100>;
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clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>, <&tbg 3>;
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#clock-cells = <1>;
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};
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tbg: tbg@13200 {
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compatible = "marvell,armada-3700-tbg-clock";
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reg = <0x13200 0x100>;
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#clock-cells = <1>;
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};
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pinctrl_nb: pinctrl-nb@13800 {
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compatible = "marvell,armada3710-nb-pinctrl",
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"syscon", "simple-mfd";
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reg = <0x13800 0x100>, <0x13C00 0x20>;
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gpionb: gpionb {
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#gpio-cells = <2>;
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gpio-ranges = <&pinctrl_nb 0 0 36>;
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gpio-controller;
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interrupts =
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<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
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};
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spi_quad_pins: spi-quad-pins {
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groups = "spi_quad";
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function = "spi";
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};
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i2c1_pins: i2c1-pins {
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groups = "i2c1";
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function = "i2c";
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};
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i2c2_pins: i2c2-pins {
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groups = "i2c2";
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function = "i2c";
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};
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uart1_pins: uart1-pins {
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groups = "uart1";
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function = "uart";
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};
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uart2_pins: uart2-pins {
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groups = "uart2";
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function = "uart";
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};
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mmc_pins: mmc-pins {
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groups = "emmc_nb";
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function = "emmc";
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};
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};
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pinctrl_sb: pinctrl-sb@18800 {
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compatible = "marvell,armada3710-sb-pinctrl",
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"syscon", "simple-mfd";
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reg = <0x18800 0x100>, <0x18C00 0x20>;
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gpiosb: gpiosb {
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#gpio-cells = <2>;
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gpio-ranges = <&pinctrl_sb 0 0 30>;
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gpio-controller;
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interrupts =
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<GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
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};
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rgmii_pins: mii-pins {
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groups = "rgmii";
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function = "mii";
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};
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smi_pins: smi-pins {
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groups = "smi";
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function = "smi";
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};
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sdio_pins: sdio-pins {
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groups = "sdio_sb";
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function = "sdio";
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};
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pcie_pins: pcie-pins {
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groups = "pcie1";
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function = "gpio";
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};
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};
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usb3: usb@58000 {
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compatible = "marvell,armada3700-xhci",
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"generic-xhci";
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reg = <0x58000 0x4000>;
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interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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usb2: usb@5e000 {
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compatible = "marvell,armada3700-ehci";
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reg = <0x5e000 0x450>;
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status = "disabled";
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};
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xor@60900 {
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compatible = "marvell,armada-3700-xor";
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reg = <0x60900 0x100
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0x60b00 0x100>;
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xor10 {
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interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
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};
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xor11 {
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interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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sdhci0: sdhci@d0000 {
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compatible = "marvell,armada-3700-sdhci",
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"marvell,sdhci-xenon";
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reg = <0xd0000 0x300
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0x1e808 0x4>;
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status = "disabled";
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};
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sdhci1: sdhci@d8000 {
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compatible = "marvell,armada-3700-sdhci",
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"marvell,sdhci-xenon";
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reg = <0xd8000 0x300
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0x17808 0x4>;
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status = "disabled";
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};
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sata: sata@e0000 {
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compatible = "marvell,armada-3700-ahci";
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reg = <0xe0000 0x2000>;
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interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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gic: interrupt-controller@1d00000 {
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compatible = "arm,gic-v3";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x1d00000 0x10000>, /* GICD */
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<0x1d40000 0x40000>; /* GICR */
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};
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eth0: neta@30000 {
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compatible = "marvell,armada-3700-neta";
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reg = <0x30000 0x20>;
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status = "disabled";
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};
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eth1: neta@40000 {
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compatible = "marvell,armada-3700-neta";
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reg = <0x40000 0x20>;
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status = "disabled";
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};
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i2c0: i2c@11000 {
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compatible = "marvell,armada-3700-i2c";
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reg = <0x11000 0x100>;
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status = "disabled";
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};
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spi0: spi@10600 {
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compatible = "marvell,armada-3700-spi";
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reg = <0x10600 0x50>;
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#address-cells = <1>;
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#size-cells = <0>;
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#clock-cells = <0>;
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spi-max-frequency = <50000000>;
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clocks = <&nb_periph_clk 7>;
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status = "disabled";
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};
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comphy: comphy@18300 {
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compatible = "marvell,mvebu-comphy", "marvell,comphy-armada-3700";
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reg = <0x18300 0x28>,
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<0x1f300 0x3d000>;
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mux-bitcount = <4>;
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mux-lane-order = <1 0 2>;
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max-lanes = <3>;
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};
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};
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pcie0: pcie@d0070000 {
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compatible = "marvell,armada-3700-pcie";
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reg = <0 0xd0070000 0 0x20000>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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num-lanes = <1>;
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status = "disabled";
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bus-range = <0 0xff>;
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/*
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* The 128 MiB address range [0xe8000000-0xf0000000] is
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* dedicated for PCIe and can be assigned to 8 windows
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* with size a power of two. Use one 64 KiB window for
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* IO at the end and the remaining seven windows
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* (totaling 127 MiB) for MEM.
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*/
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ranges = <0x82000000 0 0xe8000000
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0 0xe8000000 0 0x7f00000 /* Port 0 MEM */
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0x81000000 0 0xefff0000
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0 0xefff0000 0 0x10000>; /* Port 0 IO*/
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};
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};
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};
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