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https://github.com/brain-hackers/u-boot-brain
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bb25aca134
Convert reset manager for Gen5, Arria 10 and Stratix 10 from struct to defines. Change to get reset manager base address from DT node instead of using #define. spl_early_init() initializes the DT setup. So, move spl_early_init() to beginning of function and before get base address from DT. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
118 lines
4.6 KiB
C
118 lines
4.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2016-2017 Intel Corporation
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*/
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#ifndef _RESET_MANAGER_ARRIA10_H_
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#define _RESET_MANAGER_ARRIA10_H_
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#include <dt-bindings/reset/altr,rst-mgr-a10.h>
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void socfpga_watchdog_disable(void);
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void socfpga_reset_deassert_noc_ddr_scheduler(void);
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int socfpga_reset_deassert_bridges_handoff(void);
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void socfpga_reset_deassert_osc1wd0(void);
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int socfpga_bridges_reset(void);
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#define RSTMGR_A10_STATUS 0x00
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#define RSTMGR_A10_CTRL 0x0c
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#define RSTMGR_A10_MPUMODRST 0x20
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#define RSTMGR_A10_PER0MODRST 0x24
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#define RSTMGR_A10_PER1MODRST 0x28
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#define RSTMGR_A10_BRGMODRST 0x2c
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#define RSTMGR_A10_SYSMODRST 0x30
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#define RSTMGR_CTRL RSTMGR_A10_CTRL
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/*
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* SocFPGA Arria10 reset IDs, bank mapping is as follows:
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* 0 ... mpumodrst
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* 1 ... per0modrst
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* 2 ... per1modrst
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* 3 ... brgmodrst
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* 4 ... sysmodrst
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*/
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#define RSTMGR_EMAC0 RSTMGR_DEFINE(1, 0)
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#define RSTMGR_EMAC1 RSTMGR_DEFINE(1, 1)
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#define RSTMGR_EMAC2 RSTMGR_DEFINE(1, 2)
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#define RSTMGR_NAND RSTMGR_DEFINE(1, 5)
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#define RSTMGR_QSPI RSTMGR_DEFINE(1, 6)
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#define RSTMGR_SDMMC RSTMGR_DEFINE(1, 7)
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#define RSTMGR_DMA RSTMGR_DEFINE(1, 16)
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#define RSTMGR_SPIM0 RSTMGR_DEFINE(1, 17)
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#define RSTMGR_SPIM1 RSTMGR_DEFINE(1, 18)
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#define RSTMGR_L4WD0 RSTMGR_DEFINE(2, 0)
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#define RSTMGR_L4WD1 RSTMGR_DEFINE(2, 1)
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#define RSTMGR_L4SYSTIMER0 RSTMGR_DEFINE(2, 2)
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#define RSTMGR_L4SYSTIMER1 RSTMGR_DEFINE(2, 3)
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#define RSTMGR_SPTIMER0 RSTMGR_DEFINE(2, 4)
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#define RSTMGR_SPTIMER1 RSTMGR_DEFINE(2, 5)
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#define RSTMGR_UART0 RSTMGR_DEFINE(2, 16)
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#define RSTMGR_UART1 RSTMGR_DEFINE(2, 17)
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#define RSTMGR_DDRSCH RSTMGR_DEFINE(3, 6)
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#define ALT_RSTMGR_CTL_SWWARMRSTREQ_SET_MSK BIT(1)
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#define ALT_RSTMGR_PER0MODRST_EMAC0_SET_MSK BIT(0)
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#define ALT_RSTMGR_PER0MODRST_EMAC1_SET_MSK BIT(1)
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#define ALT_RSTMGR_PER0MODRST_EMAC2_SET_MSK BIT(2)
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#define ALT_RSTMGR_PER0MODRST_USB0_SET_MSK BIT(3)
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#define ALT_RSTMGR_PER0MODRST_USB1_SET_MSK BIT(4)
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#define ALT_RSTMGR_PER0MODRST_NAND_SET_MSK BIT(5)
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#define ALT_RSTMGR_PER0MODRST_QSPI_SET_MSK BIT(6)
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#define ALT_RSTMGR_PER0MODRST_SDMMC_SET_MSK BIT(7)
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#define ALT_RSTMGR_PER0MODRST_EMACECC0_SET_MSK BIT(8)
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#define ALT_RSTMGR_PER0MODRST_EMACECC1_SET_MSK BIT(9)
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#define ALT_RSTMGR_PER0MODRST_EMACECC2_SET_MSK BIT(10)
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#define ALT_RSTMGR_PER0MODRST_USBECC0_SET_MSK BIT(11)
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#define ALT_RSTMGR_PER0MODRST_USBECC1_SET_MSK BIT(12)
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#define ALT_RSTMGR_PER0MODRST_NANDECC_SET_MSK BIT(13)
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#define ALT_RSTMGR_PER0MODRST_QSPIECC_SET_MSK BIT(14)
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#define ALT_RSTMGR_PER0MODRST_SDMMCECC_SET_MSK BIT(15)
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#define ALT_RSTMGR_PER0MODRST_DMA_SET_MSK BIT(16)
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#define ALT_RSTMGR_PER0MODRST_SPIM0_SET_MSK BIT(17)
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#define ALT_RSTMGR_PER0MODRST_SPIM1_SET_MSK BIT(18)
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#define ALT_RSTMGR_PER0MODRST_SPIS0_SET_MSK BIT(19)
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#define ALT_RSTMGR_PER0MODRST_SPIS1_SET_MSK BIT(20)
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#define ALT_RSTMGR_PER0MODRST_DMAECC_SET_MSK BIT(21)
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#define ALT_RSTMGR_PER0MODRST_EMACPTP_SET_MSK BIT(22)
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#define ALT_RSTMGR_PER0MODRST_DMAIF0_SET_MSK BIT(24)
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#define ALT_RSTMGR_PER0MODRST_DMAIF1_SET_MSK BIT(25)
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#define ALT_RSTMGR_PER0MODRST_DMAIF2_SET_MSK BIT(26)
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#define ALT_RSTMGR_PER0MODRST_DMAIF3_SET_MSK BIT(27)
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#define ALT_RSTMGR_PER0MODRST_DMAIF4_SET_MSK BIT(28)
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#define ALT_RSTMGR_PER0MODRST_DMAIF5_SET_MSK BIT(29)
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#define ALT_RSTMGR_PER0MODRST_DMAIF6_SET_MSK BIT(30)
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#define ALT_RSTMGR_PER0MODRST_DMAIF7_SET_MSK BIT(31)
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#define ALT_RSTMGR_PER1MODRST_WD0_SET_MSK BIT(0)
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#define ALT_RSTMGR_PER1MODRST_WD1_SET_MSK BIT(1)
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#define ALT_RSTMGR_PER1MODRST_L4SYSTMR0_SET_MSK BIT(2)
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#define ALT_RSTMGR_PER1MODRST_L4SYSTMR1_SET_MSK BIT(3)
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#define ALT_RSTMGR_PER1MODRST_SPTMR0_SET_MSK BIT(4)
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#define ALT_RSTMGR_PER1MODRST_SPTMR1_SET_MSK BIT(5)
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#define ALT_RSTMGR_PER1MODRST_I2C0_SET_MSK BIT(8)
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#define ALT_RSTMGR_PER1MODRST_I2C1_SET_MSK BIT(9)
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#define ALT_RSTMGR_PER1MODRST_I2C2_SET_MSK BIT(10)
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#define ALT_RSTMGR_PER1MODRST_I2C3_SET_MSK BIT(11)
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#define ALT_RSTMGR_PER1MODRST_I2C4_SET_MSK BIT(12)
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#define ALT_RSTMGR_PER1MODRST_UART0_SET_MSK BIT(16)
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#define ALT_RSTMGR_PER1MODRST_UART1_SET_MSK BIT(17)
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#define ALT_RSTMGR_PER1MODRST_GPIO0_SET_MSK BIT(24)
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#define ALT_RSTMGR_PER1MODRST_GPIO1_SET_MSK BIT(25)
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#define ALT_RSTMGR_PER1MODRST_GPIO2_SET_MSK BIT(26)
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#define ALT_RSTMGR_BRGMODRST_H2F_SET_MSK BIT(0)
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#define ALT_RSTMGR_BRGMODRST_LWH2F_SET_MSK BIT(1)
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#define ALT_RSTMGR_BRGMODRST_F2H_SET_MSK BIT(2)
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#define ALT_RSTMGR_BRGMODRST_F2SSDRAM0_SET_MSK BIT(3)
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#define ALT_RSTMGR_BRGMODRST_F2SSDRAM1_SET_MSK BIT(4)
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#define ALT_RSTMGR_BRGMODRST_F2SSDRAM2_SET_MSK BIT(5)
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#define ALT_RSTMGR_BRGMODRST_DDRSCH_SET_MSK BIT(6)
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#define ALT_RSTMGR_HDSKEN_SDRSELFREFEN_SET_MSK BIT(0)
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#define ALT_RSTMGR_HDSKEN_FPGAMGRHSEN_SET_MSK BIT(1)
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#define ALT_RSTMGR_HDSKEN_FPGAHSEN_SET_MSK BIT(2)
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#define ALT_RSTMGR_HDSKEN_ETRSTALLEN_SET_MSK BIT(3)
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#endif /* _RESET_MANAGER_ARRIA10_H_ */
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