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20322cea64
CLKMGR_INTOSC_HZ should be 400MHz, instead of 460MHz. Removed also unused macros CLKMGR_EOSC1_HZ and CLKMGR_FPGA_CLK_HZ. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
22 lines
578 B
C
22 lines
578 B
C
/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright (C) 2016-2019 Intel Corporation <www.intel.com>
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*
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*/
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#ifndef _CLOCK_MANAGER_SOC64_
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#define _CLOCK_MANAGER_SOC64_
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const unsigned int cm_get_osc_clk_hz(void);
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const unsigned int cm_get_f2s_per_ref_clk_hz(void);
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const unsigned int cm_get_f2s_sdr_ref_clk_hz(void);
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const unsigned int cm_get_intosc_clk_hz(void);
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const unsigned int cm_get_fpga_clk_hz(void);
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#define CLKMGR_INTOSC_HZ 400000000
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/* Clock configuration accessors */
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const struct cm_config * const cm_get_default_config(void);
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#endif /* _CLOCK_MANAGER_SOC64_ */
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