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https://github.com/brain-hackers/u-boot-brain
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26e054c943
This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
21 lines
428 B
C
21 lines
428 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* (C) Copyright 2019 Xilinx, Inc,
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* Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
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*/
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#ifndef _VERSALPL_H_
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#define _VERSALPL_H_
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#include <xilinx.h>
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#define VERSAL_PM_LOAD_PDI 0x701
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#define VERSAL_PM_PDI_TYPE 0xF
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extern struct xilinx_fpga_op versal_op;
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#define XILINX_VERSAL_DESC \
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{ xilinx_versal, csu_dma, 1, &versal_op, 0, &versal_op }
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#endif /* _VERSALPL_H_ */
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