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https://github.com/brain-hackers/u-boot-brain
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c8c41d4a80
We should be using the _MEM_PHYS for LAW and TLB setup and not _MEM_BASE. While _MEM_BASE & _MEM_PHYS are normally the same, _MEM_BASE should only be used for configuring the PCI ATMU. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
194 lines
5.7 KiB
ArmAsm
194 lines
5.7 KiB
ArmAsm
/*
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* Copyright 2007 Wind River Systemes, Inc. <www.windriver.com>
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* Copyright 2007 Embedded Specialties, Inc.
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*
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* Copyright 2004 Freescale Semiconductor.
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* Copyright 2002,2003, Motorola Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <ppc_asm.tmpl>
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#include <ppc_defs.h>
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#include <asm/cache.h>
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#include <asm/mmu.h>
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#include <config.h>
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#include <mpc85xx.h>
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/*
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* TLB0 and TLB1 Entries
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*
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* Out of reset, TLB1's Entry 0 maps the highest 4K for CCSRBAR.
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* However, CCSRBAR is then relocated to CFG_CCSRBAR right after
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* these TLB entries are established.
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*
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* The TLB entries for DDR are dynamically setup in spd_sdram()
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* and use TLB1 Entries 8 through 15 as needed according to the
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* size of DDR memory.
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*
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* MAS0: tlbsel, esel, nv
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* MAS1: valid, iprot, tid, ts, tsize
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* MAS2: epn, x0, x1, w, i, m, g, e
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* MAS3: rpn, u0-u3, ux, sx, uw, sw, ur, sr
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*/
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#define entry_start \
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mflr r1 ; \
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bl 0f ;
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#define entry_end \
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0: mflr r0 ; \
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mtlr r1 ; \
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blr ;
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.section .bootpg, "ax"
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.globl tlb1_entry
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tlb1_entry:
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entry_start
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/*
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* Number of TLB0 and TLB1 entries in the following table
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*/
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.long 13
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#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR)
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/*
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* TLB0 4K Non-cacheable, guarded
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* 0xff700000 4K Initial CCSRBAR mapping
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*
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* This ends up at a TLB0 Index==0 entry, and must not collide
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* with other TLB0 Entries.
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*/
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.long FSL_BOOKE_MAS0(0, 0, 0)
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.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
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.long FSL_BOOKE_MAS2(CFG_CCSRBAR_DEFAULT, (MAS2_I|MAS2_G))
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.long FSL_BOOKE_MAS3(CFG_CCSRBAR_DEFAULT, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
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#else
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#error("Update the number of table entries in tlb1_entry")
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#endif
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/*
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* TLB0 16K Cacheable, non-guarded
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* 0xe4010000 16K Temporary Global data for initialization
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*
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* Use four 4K TLB0 entries. These entries must be cacheable
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* as they provide the bootstrap memory before the memory
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* controler and real memory have been configured.
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*
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* These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c,
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* and must not collide with other TLB0 entries.
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*/
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.long FSL_BOOKE_MAS0(0, 0, 0)
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.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
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.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR, 0)
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.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
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.long FSL_BOOKE_MAS0(0, 0, 0)
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.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
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.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 4 * 1024, 0)
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.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 4 * 1024, 0,
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(MAS3_SX|MAS3_SW|MAS3_SR))
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.long FSL_BOOKE_MAS0(0, 0, 0)
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.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
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.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 8 * 1024, 0)
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.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 8 * 1024, 0,
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(MAS3_SX|MAS3_SW|MAS3_SR))
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.long FSL_BOOKE_MAS0(0, 0, 0)
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.long FSL_BOOKE_MAS1(1, 0, 0, 0, 0)
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.long FSL_BOOKE_MAS2(CFG_INIT_RAM_ADDR + 12 * 1024, 0)
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.long FSL_BOOKE_MAS3(CFG_INIT_RAM_ADDR + 12 * 1024, 0,
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(MAS3_SX|MAS3_SW|MAS3_SR))
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/*
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* TLB 0: 16M Non-cacheable, guarded
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* 0xff800000 16M TLB for 8MB FLASH
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* Out of reset this entry is only 4K.
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*/
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.long FSL_BOOKE_MAS0(1, 0, 0)
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.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
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.long FSL_BOOKE_MAS2(CFG_FLASH_BASE, (MAS2_I|MAS2_G))
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.long FSL_BOOKE_MAS3(CFG_FLASH_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
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/*
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* TLB 1: 256M Non-cacheable, guarded
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* 0x80000000 256M PCI1 MEM First half
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*/
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.long FSL_BOOKE_MAS0(1, 1, 0)
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.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
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.long FSL_BOOKE_MAS2(CFG_PCI1_MEM_PHYS, (MAS2_I|MAS2_G))
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.long FSL_BOOKE_MAS3(CFG_PCI1_MEM_PHYS, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
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/*
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* TLB 2: 256M Non-cacheable, guarded
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* 0x90000000 256M PCI1 MEM Second half
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*/
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.long FSL_BOOKE_MAS0(1, 2, 0)
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.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
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.long FSL_BOOKE_MAS2(CFG_PCI1_MEM_PHYS + 0x10000000, (MAS2_I|MAS2_G))
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.long FSL_BOOKE_MAS3(CFG_PCI1_MEM_PHYS + 0x10000000, 0,
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(MAS3_SX|MAS3_SW|MAS3_SR))
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/*
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* TLB 3: 256M Cacheable, non-guarded
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* 0x0 256M DDR SDRAM
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*/
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#if !defined(CONFIG_SPD_EEPROM)
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.long FSL_BOOKE_MAS0(1, 3, 0)
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.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M)
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.long FSL_BOOKE_MAS2(CFG_DDR_SDRAM_BASE, 0)
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.long FSL_BOOKE_MAS3(CFG_DDR_SDRAM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
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#endif
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/*
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* TLB 4: 64M Non-cacheable, guarded
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* 0xe0000000 1M CCSRBAR
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* 0xe2000000 16M PCI1 IO
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*/
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.long FSL_BOOKE_MAS0(1, 4, 0)
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.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
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.long FSL_BOOKE_MAS2(CFG_CCSRBAR, (MAS2_I|MAS2_G))
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.long FSL_BOOKE_MAS3(CFG_CCSRBAR, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
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/*
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* TLB 5: 64M Cacheable, non-guarded
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* 0xf0000000 64M LBC SDRAM
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*/
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.long FSL_BOOKE_MAS0(1, 5, 0)
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.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M)
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.long FSL_BOOKE_MAS2(CFG_LBC_SDRAM_BASE, 0)
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.long FSL_BOOKE_MAS3(CFG_LBC_SDRAM_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
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/*
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* TLB 6: 16M Cacheable, non-guarded
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* 0xf8000000 1M 7-segment LED display
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* 0xf8100000 1M User switches
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* 0xf8300000 1M Board revision
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* 0xf8b00000 1M EEPROM
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*/
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.long FSL_BOOKE_MAS0(1, 6, 0)
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.long FSL_BOOKE_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_16M)
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.long FSL_BOOKE_MAS2(CFG_EPLD_BASE, 0)
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.long FSL_BOOKE_MAS3(CFG_EPLD_BASE, 0, (MAS3_SX|MAS3_SW|MAS3_SR))
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entry_end
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