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a462c34602
1. Define two structures mx6ul_iomux_ddr_regs and mx6ul_iomux_grp_regs. 2. Add a new function mx6ul_dram_iocfg to configure dram io. 3. Refactor MMDC1 macro, discard "#ifdef CONFIG_MX6SX". Since only mmdc0 channel exists on i.MX6SX/UL, redefine MMDC1 macro support runtime check, but not hardcoding #ifdef macros. 4. Introduce mx6ul-ddr.h, which includes the register address for DRAM IO configuration. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
46 lines
1.3 KiB
C
46 lines
1.3 KiB
C
/*
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* Copyright (C) 2015 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __ASM_ARCH_MX6UL_DDR_H__
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#define __ASM_ARCH_MX6UL_DDR_H__
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#ifndef CONFIG_MX6UL
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#error "wrong CPU"
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#endif
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#define MX6_IOM_DRAM_DQM0 0x020e0244
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#define MX6_IOM_DRAM_DQM1 0x020e0248
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#define MX6_IOM_DRAM_RAS 0x020e024c
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#define MX6_IOM_DRAM_CAS 0x020e0250
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#define MX6_IOM_DRAM_CS0 0x020e0254
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#define MX6_IOM_DRAM_CS1 0x020e0258
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#define MX6_IOM_DRAM_SDWE_B 0x020e025c
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#define MX6_IOM_DRAM_SDODT0 0x020e0260
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#define MX6_IOM_DRAM_SDODT1 0x020e0264
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#define MX6_IOM_DRAM_SDBA0 0x020e0268
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#define MX6_IOM_DRAM_SDBA1 0x020e026c
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#define MX6_IOM_DRAM_SDBA2 0x020e0270
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#define MX6_IOM_DRAM_SDCKE0 0x020e0274
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#define MX6_IOM_DRAM_SDCKE1 0x020e0278
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#define MX6_IOM_DRAM_SDCLK_0 0x020e027c
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#define MX6_IOM_DRAM_SDQS0 0x020e0280
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#define MX6_IOM_DRAM_SDQS1 0x020e0284
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#define MX6_IOM_DRAM_RESET 0x020e0288
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#define MX6_IOM_GRP_ADDDS 0x020e0490
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#define MX6_IOM_DDRMODE_CTL 0x020e0494
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#define MX6_IOM_GRP_B0DS 0x020e0498
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#define MX6_IOM_GRP_DDRPK 0x020e049c
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#define MX6_IOM_GRP_CTLDS 0x020e04a0
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#define MX6_IOM_GRP_B1DS 0x020e04a4
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#define MX6_IOM_GRP_DDRHYS 0x020e04a8
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#define MX6_IOM_GRP_DDRPKE 0x020e04ac
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#define MX6_IOM_GRP_DDRMODE 0x020e04b0
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#define MX6_IOM_GRP_DDR_TYPE 0x020e04b4
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#endif /*__ASM_ARCH_MX6SX_DDR_H__ */
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