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1b811e285c
Define two structure mx6sl_iomux_ddr_regs and mx6sl_iomux_grp_regs. Add a new function mx6sl_dram_iocfg to configure dram io. Add header file to define macros for register address. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
46 lines
1.1 KiB
C
46 lines
1.1 KiB
C
/*
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* Copyright (C) 2015 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __ASM_ARCH_MX6SL_DDR_H__
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#define __ASM_ARCH_MX6SL_DDR_H__
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#ifndef CONFIG_MX6SL
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#error "wrong CPU"
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#endif
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#define MX6_IOM_DRAM_CAS_B 0x020e0300
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#define MX6_IOM_DRAM_CS0_B 0x020e0304
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#define MX6_IOM_DRAM_CS1_B 0x020e0308
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#define MX6_IOM_DRAM_DQM0 0x020e030c
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#define MX6_IOM_DRAM_DQM1 0x020e0310
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#define MX6_IOM_DRAM_DQM2 0x020e0314
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#define MX6_IOM_DRAM_DQM3 0x020e0318
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#define MX6_IOM_DRAM_RAS_B 0x020e031c
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#define MX6_IOM_DRAM_RESET 0x020e0320
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#define MX6_IOM_DRAM_SDBA0 0x020e0324
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#define MX6_IOM_DRAM_SDBA1 0x020e0328
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#define MX6_IOM_DRAM_SDBA2 0x020e032c
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#define MX6_IOM_DRAM_SDCKE0 0x020e0330
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#define MX6_IOM_DRAM_SDCKE1 0x020e0334
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#define MX6_IOM_DRAM_SDCLK0_P 0x020e0338
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#define MX6_IOM_DRAM_ODT0 0x020e033c
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#define MX6_IOM_DRAM_ODT1 0x020e0340
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#define MX6_IOM_DRAM_SDQS0_P 0x020e0344
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#define MX6_IOM_DRAM_SDQS1_P 0x020e0348
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#define MX6_IOM_DRAM_SDQS2_P 0x020e034c
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#define MX6_IOM_DRAM_SDQS3_P 0x020e0350
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#define MX6_IOM_DRAM_SDWE_B 0x020e0354
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#endif /*__ASM_ARCH_MX6SL_DDR_H__ */
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