Dave Liu 80ee3ce6d7 fsl-ddr: update the bit mask for DDR3 controller ... According to the latest 8572 UM, the DDR3 controller is expanding the bit mask, and we use the extend ACTTOPRE mode when tRAS more than 19 MCLK. Signed-off-by: Dave Liu <daveliu@freescale.com>		2009-01-23 17:03:13 -06:00
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common_timing_params.h	FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code.	2008-08-27 02:05:58 +02:00
ctrl_regs.c	fsl-ddr: update the bit mask for DDR3 controller	2009-01-23 17:03:13 -06:00
ddr.h	Pass dimm parameters to populate populate controller options	2008-10-18 21:54:04 +02:00
ddr1_dimm_params.c	FSL DDR: Add DDR1 DIMM paramter support	2008-08-27 02:05:59 +02:00
ddr2_dimm_params.c	FSL DDR: Add DDR2 DIMM paramter support	2008-08-27 02:06:00 +02:00
lc_common_dimm_params.c	FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code.	2008-08-27 02:05:58 +02:00
main.c	fsl ddr skip interleaving if not supported.	2008-12-03 22:47:19 -06:00
Makefile	FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code.	2008-08-27 02:05:58 +02:00
options.c	fsl ddr skip interleaving if not supported.	2008-12-03 22:47:19 -06:00
util.c	FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code.	2008-08-27 02:05:58 +02:00